Key Takeaways & Executive Findings
- •• • The NTT-based decomposition reduces FPGA hardware memory consumption by 50% compared with the conventional monolithic iterative model, directly enabling deployment of complex multi-switch topologies on resource-constrained HIL platforms without matrix storage overflow. • • The predictor-corrector switch-state mechanism eliminates the iterative algebraic-loop solver entirely, allowing a 70 ns real-time simulation step for an LLC resonant converter—an order-of-magnitude improvement over the microsecond-scale steps achievable with iterative NTT plus Gauss-Jordan inversion. • • Offline validation against MATLAB/Simulink yields a computational error not exceeding 0.1%, confirming that the tearing-point equivalent circuits preserve numerical fidelity of the high-order nodal formulation. • • Real-time FPGA waveforms match the hardware experimental platform within 5% error, and the method suppresses the zero-crossing oscillation of resonant current that arises in delay-injection decoupled models when the converter enters the disabled (no gate signal) mode.
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Abstract
Complex converter topologies operating at elevated switching frequencies impose severe hardware resource and simulation-step constraints on FPGA-based hardware-in-the-loop (HIL) real-time simulation. Conventional binary-resistor modeling requires storing a distinct nodal admittance matrix for every switch state and resolving the algebraic loop between switch voltage and switch state through iterative computation, which inflates memory consumption and renders the achievable time step unpredictable. This work proposes a network tearing technique (NTT) that decomposes the high-order nodal voltage equations of the converter into multiple low-order subsystems linked only through equivalent circuits at tearing points, permitting independent modeling of each subsystem and a substantial reduction in stored matrix coefficients. The switch-state decision process is simplified and reformulated as a predictor-corrector scheme that replaces iterative solving, eliminating zero-crossing oscillation while shortening the critical solution path. An LLC resonant converter was modeled offline and validated against MATLAB/Simulink with a computational error not exceeding 0.1%. The FPGA implementation, using lookup-table coefficient updates with dimensioned hardware logic and variable bit widths, achieves a 70 ns simulation step. Real-time waveforms deviate from the hardware experimental platform by no more than 5%, and hardware memory consumption is reduced by 50% relative to the monolithic iterative model.
1. Introduction
FPGA-based hardware-in-the-loop simulation is the only viable route to nanosecond-scale real-time emulation of power electronic converters, yet its finite on-chip memory and logic resources collide directly with the modeling demands of modern high-frequency, multi-switch topologies. The binary-resistor model offers superior accuracy and topological generality compared with ideal-switch and associated-discrete-circuit formulations, but it requires storing a nodal admittance matrix for every switch state and resolving the algebraic loop between switch voltage and switch state through iterative computation. The number of iterations needed for convergence cannot be derived analytically; it depends on topology, circuit parameters, and discretization method, so the achievable simulation step remains unpredictable and the model cannot be scaled to converters with large switch counts.
Prior decoupling strategies each carry a specific penalty. Delay-injection methods restrict tearing-point selection to internal state variables, degrade numerical stability, and—critically—break the feedback path between subsystems so that switch states cannot be judged correctly, producing zero-crossing oscillation in the resonant current when the converter is disabled. Topology-aware matrix partitioning still requires assembling the full system matrix and optimizes only the real-time inversion, leaving the switch-state iteration untouched. Network tearing combined with Gauss-Jordan inversion remains trapped at microsecond-scale steps. Direct mapping of switch states becomes intractable as switch count grows and fails to identify the state of bridge arms with no gate enable. This work addresses the bottleneck by tearing the converter into independently modeled low-order subsystems and replacing iterative switch-state resolution with a predictor-corrector scheme, demonstrated on an LLC resonant converter at a 70 ns step.
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WANG Shinan, GUO Xizheng, WANG Zihao, YIN Yongjie, YUAN Bo (2026). Real-Time Simulation Modeling Method for Power Electronic Converters Based on Network Tearing. Power Automation Equipment. https://doi.org/10.16081/j.epae.202605012
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Frequently Asked Questions
How does the predictor-corrector scheme guarantee correct switch-state identification when a bridge arm has no gate enable signal, a condition where direct mapping methods are known to fail?
The predictor stage evaluates switch voltage from the previous-step nodal solution, and the corrector stage updates the state using the current-step nodal voltage computed with the predicted admittance matrix. Because the decision is driven by measured switch voltage rather than by gate logic alone, the disabled bridge-arm condition is resolved correctly. This is the mechanism that suppresses the zero-crossing oscillation observed in delay-injection decoupled models, where each subsystem judges switch state independently from historical inputs and no feedback loop forms between subsystems.
What is the measured accuracy penalty of the network tearing decomposition relative to the full-order nodal model?
Offline comparison against a MATLAB/Simulink reference model of the LLC resonant converter shows a computational error not exceeding 0.1%. The tearing-point equivalent circuits therefore introduce negligible numerical error while permitting independent low-order subsystem modeling. In real-time operation on the FPGA platform, the simulated waveforms deviate from the hardware experimental platform by no more than 5%, which bounds the combined discretization, quantization, and tearing error under actual switching conditions.
Does the 50% memory reduction hold as switch count and topology complexity increase, or is it specific to the LLC case?
The reduction follows from the decomposition itself: the monolithic binary-resistor model stores a nodal admittance matrix for each switch state, so memory scales with the full system order and the number of switch combinations. Tearing partitions the high-order nodal equation into multiple low-order subsystems, each with its own small coefficient set, and the reported 50% hardware memory saving for the LLC converter reflects this structural scaling rather than a topology-specific artifact. The lookup-table coefficient update mechanism further constrains storage by replacing on-line matrix computation with precomputed entries.
What limits the minimum achievable simulation step below 70 ns, and is the predictor-corrector path the binding constraint?
The 70 ns step is set by the critical solution path after iteration is removed. The predictor-corrector scheme shortens this path by eliminating the convergence loop whose iteration count cannot be bounded analytically, but the remaining path includes nodal equation evaluation, lookup-table coefficient retrieval, and switch-voltage computation. Variable bit-width design and hardware logic partitioning were applied specifically to fit this path within 70 ns on the target FPGA. Pushing below this threshold would require further shortening of the nodal solve or higher clock rates, not changes to the switch-state mechanism.
Can this method be applied to converters with substantially higher switch counts, such as three-level or modular multilevel topologies, without re-deriving the tearing points?
The method is formulated for arbitrary converter topologies: the binary-resistor equivalent is applied to switch elements, energy-storage elements are discretized, and the resulting nodal voltage equations are torn at selected decoupling points into low-order subsystems. Tearing-point selection is not restricted to internal state variables as in delay-injection methods, which widens the admissible decoupling locations. Each subsystem is modeled independently and linked only through equivalent circuits at the tearing points, so scaling to higher switch counts increases the number of subsystems rather than the order of any single stored matrix.
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