Key Takeaways & Executive Findings
- •• • The empirical computational cost model, built on floating-point operation counts of matrix LU decomposition, achieves a simulation time fitting goodness-of-fit R² > 0.97 across three large-scale AC/DC distribution network test cases (IEEE 34-node, IEEE 123-node, European LV). This high predictive accuracy enables reliable pre-simulation estimation of parallel overhead, eliminating trial-and-error resource allocation in engineering deployment. • • Under the optimal partition configuration determined by the proposed screening strategy, the parallel speedup ratio reaches 12.11–15.77, substantially exceeding conventional natural partitioning schemes. This performance level directly translates to reduced simulation wall-clock time for transient stability assessment, allowing grid operators to evaluate high-penetration power electronic scenarios within operational planning windows. • • The heterogeneous weighted graph model maps matrix dimensions of diverse device models (converters, photovoltaics, energy storage) to node weights, addressing the device heterogeneity that causes load imbalance in traditional degree-based partitioning. This graph-theoretic representation captures computational complexity differences that prior methods ignored, preventing partition bottlenecks that degrade parallel efficiency. • • The multi-objective partitioning scheme simultaneously minimizes tie-line variable count and balances partition computational overhead, a dual consideration absent in transmission-grid-oriented partitioning algorithms. For AC/DC distribution networks with short lines and tight electrical coupling, this joint optimization reduces both per-step communication overhead and serial bottleneck time in the boundary coordination equation solve.
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Abstract
The increasing penetration of power electronic devices in AC/DC distribution networks imposes stringent computational demands on electromagnetic transient (EMT) parallel simulation. Conventional transmission-line delay decoupling methods are ill-suited to the strong electrical coupling characteristic of such networks. This paper proposes a non-delay decoupling parallel simulation acceleration framework based on heterogeneous weighted graph partitioning. An empirical computational cost evaluation model for each parallel decoupling stage is established, and a heterogeneous weighted graph model is constructed to precisely characterize the simulation computational complexity of AC/DC distribution network components, mapping matrix dimensions of device mathematical models to graph node weights. A multi-objective graph partitioning scheme is formulated that simultaneously balances partition computational overhead and minimizes the number of tie-line variables, complemented by an optimal partition number screening strategy. Simulation validation is conducted on three large-scale AC/DC distribution network composite test cases: IEEE 34-node, IEEE 123-node, and European Low Voltage (European LV) systems, all retrofitted with DC sections. Results demonstrate that the proposed empirical computational cost model achieves a simulation time fitting goodness-of-fit R² > 0.97, indicating high predictive accuracy. Under optimal partition configuration, the proposed method attains parallel speedup ratios of 12.11–15.77, significantly outperforming conventional natural partitioning schemes and effectively enhancing the EMT parallel simulation efficiency of AC/DC distribution networks.
1. Introduction
Electromagnetic transient (EMT) simulation of AC/DC distribution networks with high power electronic device penetration faces a computational bottleneck that conventional parallelization strategies cannot resolve. Existing delay decoupling methods exploit wave propagation delays on long transmission lines to naturally partition networks, but AC/DC distribution networks exhibit short lines, radial or weakly meshed topologies, and strong electrical coupling—conditions that render delay-based decoupling inapplicable. Artificial delay insertion methods introduce accuracy degradation and stability risks. Non-delay decoupling approaches, such as the compensation method (CM) and diakoptics-based tearing, partition the network matrix directly but require balanced partition strategies to achieve computational efficiency. Prior graph partitioning research, largely developed for AC transmission networks, assumes homogeneous device models and uniform computational load per node, an assumption that collapses when confronted with the heterogeneous device mix of converters, photovoltaics, and energy storage in AC/DC distribution networks.
This work addresses the partitioning bottleneck by constructing a heterogeneous weighted graph that encodes the actual simulation computational complexity of each device into node weights, derived from matrix dimensions of device mathematical models. The proposed framework integrates an empirical computational cost evaluation model for each parallel decoupling stage, a multi-objective graph partitioning algorithm that balances partition overhead and minimizes tie-line variables, and an optimal partition number screening strategy. Validation on IEEE 34-node, IEEE 123-node, and European LV AC/DC retrofitted systems demonstrates R² > 0.97 for simulation time prediction and parallel speedup ratios of 12.11–15.77, establishing a quantitative basis for hardware resource deployment in practical engineering.
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LUO Zhenyang, XU Jin, ZHAN Haisong, WU Pan, WANG Keyou (2026). Heterogeneous Weighted Graph Partitioning and Decoupling Optimization Strategy for Electromagnetic Transient Parallel Simulation of AC/DC Distribution Networks. Power Automation Equipment. https://doi.org/10.16081/j.epae.202607002
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Frequently Asked Questions
What specific computational bottleneck in AC/DC distribution network EMT simulation does the heterogeneous weighted graph partitioning address, and how is its effectiveness quantified?
The bottleneck arises from strong electrical coupling and device heterogeneity: traditional delay decoupling fails because distribution lines are too short for wave propagation delays, while conventional graph partitioning assumes uniform node weights and ignores the computational complexity differences among converters, photovoltaics, and energy storage. The proposed method maps matrix dimensions of each device model to graph node weights, enabling balanced partition overhead and minimized tie-line variables. Quantitatively, the empirical cost model achieves R² > 0.97 for simulation time prediction, and the parallel speedup ratio reaches 12.11–15.77 under optimal partitioning, compared to significantly lower performance with natural partitioning schemes.
How does the proposed method ensure numerical stability and accuracy when using non-delay decoupling, given that artificial delay insertion methods are known to degrade accuracy?
The method employs the compensation method (CM) for non-delay decoupling, which solves the network equations exactly without inserting artificial delays. The CM partitions the network into subnetworks and a tie-line system, solves subnetwork responses in parallel, then serially solves the boundary coordination equation for tie-line voltages, and finally back-substitutes to obtain the full network solution. This preserves the exact mathematical equivalence of the original network equations, avoiding the accuracy and stability penalties associated with delay insertion. The validation on three test systems confirms the simulation results match the original network behavior, with the speedup achieved purely through parallelization rather than approximation.
What are the scalability limits of the proposed partitioning strategy when applied to larger distribution networks with thousands of nodes?
The method's scalability depends on the graph partitioning algorithm's ability to handle large graphs and the parallel hardware's core count. The optimal partition number screening strategy captures the trade-off between parallel task count and simulation time, identifying the point where communication and synchronization overhead outweigh additional parallelism. For the tested systems (IEEE 34, IEEE 123, European LV), speedup ratios of 12.11–15.77 were achieved, indicating effective utilization of 12–16 parallel tasks. Beyond this range, the serial tie-line solve and communication overhead become dominant. The framework provides a pre-simulation estimation to determine the optimal partition number for a given hardware configuration, preventing over-partitioning that degrades efficiency.
How does the heterogeneous weighted graph model account for the different computational costs of various power electronic devices, and what empirical parameters are used?
The model maps the matrix dimension of each device's mathematical model to a graph node weight. For example, a converter with a larger state-space matrix receives a higher weight than a simple load. The empirical computational cost evaluation model is based on floating-point operation counts of matrix LU decomposition, which dominates the node voltage equation solve (80–97% of total simulation time). The model was validated across three test systems, achieving R² > 0.97 for predicting simulation time from graph weights. This allows the partitioning algorithm to balance the actual computational load rather than assuming uniform node costs.
What is the industrial impact of achieving a parallel speedup ratio of 12.11–15.77 for EMT simulation of AC/DC distribution networks?
A speedup of 12–16 times reduces simulation wall-clock time from hours to minutes for large-scale AC/DC distribution networks, enabling transient analysis within operational planning and real-time assessment windows. This is critical for evaluating high-penetration power electronic scenarios, where detailed EMT simulation is required to capture fast dynamics but conventional serial simulation is prohibitively slow. The speedup directly translates to increased engineering productivity, faster design iteration for converter-dominated systems, and the ability to perform contingency analysis that would otherwise be infeasible. The pre-simulation optimal partition screening further reduces deployment cost by providing quantitative hardware sizing guidance.
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