Key Takeaways & Executive Findings
- •• • FPGA-based PWM averaging achieves nanosecond-level sampling resolution, increasing sampling points per switching period from a few (under microsecond steps) to 2,500–10,000 points, reducing duty cycle jitter and numerical error accumulation that otherwise cause instability in HIL systems. • • The averaging technique eliminates frequent topology updates and state matrix reconstructions, lowering real-time computational load and enabling stable operation under strict real-time constraints with microsecond-level simulation steps, as validated by industrial-grade controller tests. • • The platform successfully performed two typical operating condition tests (steady-state and HVRT) on an industrial grid-connected controller, identifying non-compliant metrics that were fed back to the manufacturer for strategy optimization, demonstrating practical industrial applicability. • • The UREP+FPGA architecture provides a domestic alternative to RTDS and RT-LAB, offering a feasible technical path for high-frequency controller HIL testing without the modeling complexity and resource constraints associated with FPGA partitioning in existing commercial solutions.
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Abstract
Real-time constraints prevent CPU-based electromagnetic transient simulators from accurately sampling high-frequency PWM signals at microsecond step sizes, leading to insufficient HIL test precision and even instability of the closed-loop system. This paper introduces a PWM averaging technique to construct a novel UREP (electromagnetic transient real-time simulator) + FPGA hardware-in-the-loop test platform. To achieve accurate PWM acquisition, the FPGA's nanosecond-level clock resolution increases the number of sampling points within a single switching period from a few points under microsecond simulation steps to several thousand points. The FPGA implements fixed-step PWM averaging, converting discrete switching states into continuous duty cycles that serve as control signals for the UREP-side inverter average model. This technique avoids frequent topology updates and state matrix reconstructions triggered by switching events, reduces high real-time computational resource consumption, improves numerical stability of the in-loop system, and enhances HIL test accuracy under large-step real-time constraints. Simulation cases and industrial-grade controller HIL tests verify the platform's feasibility and accuracy. The platform provides an efficient, reproducible verification scheme for photovoltaic controller control strategies and offers a feasible technical path for domestic electromagnetic transient real-time simulation platforms to conduct high-frequency controller HIL tests.
1. Introduction
Existing commercial real-time simulators, such as RTDS and OPAL-RT, face significant bottlenecks when testing high-frequency photovoltaic controllers. RTDS employs a Mainstep/Substep architecture that requires strict subnetwork size control and model simplification to maintain real-time performance as switching frequencies increase, drastically raising modeling and debugging complexity. OPAL-RT maps power circuits to FPGAs via the electric hardware solver (eHS), but its FPGA resource occupancy is strongly correlated with model scale, topology complexity, and target step size, forcing additional modeling accuracy trade-offs and limiting scalability. These limitations stem from the fundamental conflict between microsecond-level simulation steps and the need to accurately capture PWM signals with switching frequencies up to tens of kHz.
To address this bottleneck, this work proposes a UREP+FPGA hardware-in-the-loop test platform that leverages PWM averaging. The FPGA captures PWM signals with nanosecond resolution, yielding thousands of sampling points per switching period, and performs fixed-step averaging to convert discrete switching states into continuous duty cycles. These duty cycles drive an inverter average model on the UREP side, avoiding frequent topology updates and state matrix reconstructions. The platform was validated through simulation cases and industrial-grade controller HIL tests under steady-state and HVRT conditions, demonstrating improved numerical stability and test accuracy under strict real-time constraints.
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XU Tao, JIANG Chunhong, KUANG Weixing, HAO Zhenghang, CHEN Zhuo, XIONG Guojiang (2026). Hardware-in-the-Loop Test Platform for Photovoltaic High-Frequency Controllers Based on UREP + FPGA. Power Automation Equipment. https://doi.org/10.16081/j.epae.202605021
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Frequently Asked Questions
What specific sampling errors occur when using CPU-based simulators for high-frequency PWM acquisition, and how does the proposed method mitigate them?
CPU-based simulators with microsecond steps produce pulse width underestimation, overestimation, and event miss-detection, leading to duty cycle jitter and numerical error accumulation that can cause instability. The FPGA-based approach samples at nanosecond resolution, achieving 2,500–10,000 points per switching period, which reduces the maximum averaging error to ≤2 clock periods (typically 5–10 ns), effectively eliminating these errors.
How does the PWM averaging technique affect the numerical stability and computational load of the HIL system?
By converting discrete switching states into continuous duty cycles, the technique avoids frequent topology updates and state matrix reconstructions triggered by switching events. This reduces real-time computational resource consumption and improves numerical stability, as demonstrated by stable operation under microsecond simulation steps with industrial-grade controllers.
What are the limitations of the inverter average model used in this platform, and for what applications is it suitable?
The average model cannot capture device-level transient switching behavior, but it is well-suited for controller design and verification, particularly for grid-connected control strategy testing. The platform successfully tested steady-state and HVRT conditions, identifying non-compliant metrics for optimization.
How does the UREP+FPGA platform compare to commercial solutions like RTDS and OPAL-RT in terms of scalability and modeling complexity?
Unlike RTDS, which requires strict subnetwork size control and model simplification, and OPAL-RT, which faces FPGA resource constraints and partitioning needs, the UREP+FPGA platform avoids topology updates and matrix reconstructions, reducing modeling and debugging complexity while maintaining real-time performance for high-frequency controllers.
What industrial validation was performed, and what were the key findings?
The platform was tested with an industrial grid-connected controller under steady-state and HVRT conditions. Non-compliant metrics were identified and fed back to the manufacturer for strategy optimization, confirming the platform's practical applicability and accuracy for high-frequency controller HIL testing.
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