Real-Time Simulation Modeling Method for Power Electronic Converters Based on Network Tearing
Complex converter topologies operating at elevated switching frequencies impose severe hardware resource and simulation-step constraints on FPGA-based hardware-in-the-loop (HIL) real-time simulation. Conventional binary-resistor modeling requires storing a distinct nodal admittance matrix for every switch state and resolving the algebraic loop between switch voltage and switch state through iterative computation, which inflates memory consumption and renders the achievable time step unpredictable. This work proposes a network tearing technique (NTT) that decomposes the high-order nodal voltage equations of the converter into multiple low-order subsystems linked only through equivalent circuits at tearing points, permitting independent modeling of each subsystem and a substantial reduction in stored matrix coefficients. The switch-state decision process is simplified and reformulated as a predictor-corrector scheme that replaces iterative solving, eliminating zero-crossing oscillation while shortening the critical solution path. An LLC resonant converter was modeled offline and validated against MATLAB/Simulink with a computational error not exceeding 0.1%. The FPGA implementation, using lookup-table coefficient updates with dimensioned hardware logic and variable bit widths, achieves a 70 ns simulation step. Real-time waveforms deviate from the hardware experimental platform by no more than 5%, and hardware memory consumption is reduced by 50% relative to the monolithic iterative model.