Real-Time Simulation Modeling Method for Power Electronic Converters Based on Network Tearing

• • The NTT-based decomposition reduces FPGA hardware memory consumption by 50% compared with the conventional monolithic iterative model, directly enabling deployment of complex multi-switch topologies on resource-constrained HIL platforms without matrix storage overflow. • • The predictor-corrector switch-state mechanism eliminates the iterative algebraic-loop solver entirely, allowing a 70 ns real-time simulation step for an LLC resonant converter—an order-of-magnitude improvement over the microsecond-scale steps achievable with iterative NTT plus Gauss-Jordan inversion. • • Offline validation against MATLAB/Simulink yields a computational error not exceeding 0.1%, confirming that the tearing-point equivalent circuits preserve numerical fidelity of the high-order nodal formulation. • • Real-time FPGA waveforms match the hardware experimental platform within 5% error, and the method suppresses the zero-crossing oscillation of resonant current that arises in delay-injection decoupled models when the converter enters the disabled (no gate signal) mode.