• • FPGA-based PWM averaging achieves nanosecond-level sampling resolution, increasing sampling points per switching period from a few (under microsecond steps) to 2,500–10,000 points, reducing duty cycle jitter and numerical error accumulation that otherwise cause instability in HIL systems.
• • The averaging technique eliminates frequent topology updates and state matrix reconstructions, lowering real-time computational load and enabling stable operation under strict real-time constraints with microsecond-level simulation steps, as validated by industrial-grade controller tests.
• • The platform successfully performed two typical operating condition tests (steady-state and HVRT) on an industrial grid-connected controller, identifying non-compliant metrics that were fed back to the manufacturer for strategy optimization, demonstrating practical industrial applicability.
• • The UREP+FPGA architecture provides a domestic alternative to RTDS and RT-LAB, offering a feasible technical path for high-frequency controller HIL testing without the modeling complexity and resource constraints associated with FPGA partitioning in existing commercial solutions.