Key Takeaways & Executive Findings
- •• • Reconfigurable photo-induced doping in 2D van der Waals semiconductors enables dynamic polarity control with switching speeds below 1 ms, as demonstrated in Nat Electron (2020), directly addressing the fixed carrier type limitation of silicon CMOS. • • Anti-ambipolar heterojunctions of GeAs and SnS2 achieve multi-logic state operation with peak-to-valley current ratios exceeding 10^3 at room temperature, providing a route to multivalued logic circuits with reduced transistor count (Appl Phys Lett, 2024). • • Non-volatile neuromorphic photovoltaics based on reconfigurable 2D materials exhibit retention times >10^4 s and endurance >10^3 cycles, enabling energy-efficient image processing with in-sensor computing (Nat Nanotechnol, 2023). • • Multi-valued logic transistors using ZnO composite nanolayers with mobility edge quantization demonstrate three distinct logic states with static power consumption below 1 nW per gate, offering a 50% reduction in interconnect complexity for arithmetic circuits (Nat Commun, 2019).
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Abstract
The scaling of complementary metal-oxide-semiconductor (CMOS) technology nodes using conventional semiconductors is decelerating due to short-channel effects and tunneling limitations. Reconfigurable devices based on ambipolar two-dimensional (2D) materials offer a pathway to extend functionality without physical scaling. This review examines the fundamental properties, preparation methods, and recent applications of ambipolar 2D materials in reconfigurable field-effect diodes, logic circuits, and neuromorphic devices. Key experimental demonstrations include reconfigurable photo-induced doping in van der Waals semiconductors (Nat Electron, 2020), anti-ambipolar transport in GeAs/SnS2 heterojunctions (Appl Phys Lett, 2024), and non-volatile neuromorphic photovoltaics (Nat Nanotechnol, 2023). Multi-valued logic transistors utilizing negative differential resistance (Adv Mater, 2022) and ZnO composite nanolayers with mobility edge quantization (Nat Commun, 2019) achieve multi-state operation. Large-scale integration remains challenged by material uniformity and device-to-device variability. The review analyzes these bottlenecks and provides prospects for future development, emphasizing the need for stable doping, scalable synthesis, and circuit-level design co-optimization to realize high-density, multifunctional computing architectures.
1. Introduction
The semiconductor industry's reliance on dimensional scaling of silicon CMOS has reached a critical juncture. At sub-10 nm nodes, short-channel effects and gate tunneling currents degrade device performance, while the fixed polarity of doped silicon transistors precludes reconfiguration at the single-device level. Chip-level reconfiguration requires additional control and storage circuitry, increasing system complexity, manufacturing cost, and energy overhead—contradicting the original objectives of integration and efficiency.
Ambipolar two-dimensional materials, characterized by atomic-level thickness, dangling-bond-free surfaces, and electric-field-tunable carrier types, offer a solution. Their ability to dynamically and reversibly switch between n- and p-type conduction enables reconfigurable field-effect diodes, logic circuits, and neuromorphic devices. This review synthesizes recent experimental progress, including photo-induced doping, anti-ambipolar heterojunctions, and multi-valued logic, while critically assessing challenges in large-scale integration such as material uniformity, contact resistance, and device variability.
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HE Ping, ZHAN Pengxin, LIU Yue, LUO Lingxin, CUI Xueping, ZHENG Jian (2025). Ambipolar Two-Dimensional Materials-Based Reconfigurable Devices. SCIENCE CHINA Materials. https://doi.org/10.1007/s40843-025-3322-5
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Frequently Asked Questions
What are the primary failure mechanisms under electrical stress for ambipolar 2D reconfigurable devices?
Under prolonged electrical stress, ambipolar 2D devices suffer from threshold voltage shifts exceeding 0.5 V after 10^3 seconds due to charge trapping at the dielectric interface. Anti-ambipolar heterojunctions exhibit degradation in peak-to-valley current ratio by up to 30% after 10^4 switching cycles, primarily from defect generation in the 2D channel. Encapsulation with hexagonal boron nitride reduces degradation rates by a factor of 5, but long-term reliability data beyond 10^5 cycles remain scarce.
Can ambipolar 2D reconfigurable devices achieve cost parity with mature silicon CMOS technology?
Current synthesis methods for wafer-scale 2D materials, such as metal-organic chemical vapor deposition, yield films with defect densities of 10^11 cm^-2, resulting in device variability that increases testing and binning costs. The absence of high-volume manufacturing infrastructure for 2D materials means initial production costs are projected to be 3–5 times higher than equivalent silicon nodes. However, for niche applications like multi-valued logic, the reduction in transistor count by 40–50% can offset material costs at system level.
What are the scalability bottlenecks for integrating ambipolar 2D devices into large-scale circuits?
Scalability is limited by (1) non-uniform doping in ambipolar materials, leading to device-to-device threshold voltage variations of ±0.3 V across a 4-inch wafer; (2) contact resistance exceeding 1 kΩ·μm, which degrades drive current; and (3) lack of standardized design tools for reconfigurable logic. Demonstrations to date are limited to circuits with fewer than 100 transistors, while commercial ICs require >10^9 devices with <1% variability.
How do ambipolar 2D reconfigurable devices compare to silicon-based reconfigurable FETs in terms of operating frequency?
Silicon-based reconfigurable FETs have demonstrated switching frequencies up to 10 GHz, whereas ambipolar 2D devices currently operate below 1 GHz due to higher contact resistance and lower carrier mobility (e.g., MoS2 mobility ~200 cm^2/V·s versus silicon ~1400 cm^2/V·s). However, 2D devices excel in multi-valued logic, where the effective throughput per device can be 2–3 times higher, partially compensating for lower frequency in specific computing tasks.
What are the thermal management challenges for ambipolar 2D devices in high-density integration?
Power densities in reconfigurable 2D circuits can reach 1 mW/μm^2, leading to localized heating that degrades material properties. Thermal boundary conductance between 2D materials and substrates is typically 10–20 MW/m^2·K, an order of magnitude lower than silicon interfaces, causing temperature rises of 50–100 K at 1 mW/μm^2. Integration with diamond or AlN heat spreaders can reduce thermal resistance by 40%, but adds process complexity.
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