Key Takeaways & Executive Findings
- •• • At a 50 μs simulation step, the proposed blocking-state prediction method holds computational error within 3‰–7‰, whereas conventional direct prediction suffers severe accuracy degradation once diode states change multiple times within a single step; this threshold is decisive because 50 μs is the practical ceiling for multi-core CPU real-time simulation of large-scale MMC grids. • • Single-step total computation time is constrained to approximately 22.23 μs on a multi-core CPU parallel architecture with per-arm task allocation to independent cores, leaving a 27.77 μs margin against the 50 μs real-time deadline and confirming that constraint-based prediction does not introduce rollback or interpolation overhead. • • Prediction failure rate is significantly lower than that of the traditional direct prediction method under identical 50 μs conditions, directly addressing the over-shoot and numerical oscillation mechanisms that arise when natural diode commutation instants fall inside a fixed time step. • • The method eliminates dependence on FPGA high-speed clock signals and CPU–FPGA timestamp interaction required by RTLAB-style error compensation, and avoids the virtual energy loss inherent to inductance/capacitance equivalent diode models whose error grows monotonically with step size.
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Abstract
Real-time electromagnetic transient simulation of modular multilevel converters (MMCs) on multi-core CPU platforms at large time steps is constrained by the difficulty of predicting diode conduction states during blocking operation. Conventional direct prediction methods sample node voltages at the previous time step and extrapolate the next switching state; at 50 μs, however, multiple natural commutation events can occur within a single step, producing over-shoot, numerical oscillation, and elevated prediction failure rates. This work proposes a blocking-state prediction method grounded in the internal topological and electrical constraints of submodules. Diodes exhibiting identical behavior under blocking are aggregated into a unified equivalent circuit, and a constraint-based state prediction mechanism with enhanced robustness is constructed, eliminating reliance on high-speed FPGA timestamping or variable-step rollback. Offline and real-time simulations on the ADPSS platform demonstrate that at a 50 μs step the proposed method maintains computational error within 3‰–7‰, substantially reduces prediction failure probability relative to direct prediction, and completes a single simulation step in approximately 22.23 μs on a multi-core CPU architecture, satisfying the 50 μs real-time constraint. The method provides a viable pathway for efficient CPU-based real-time simulation of large-scale MMC systems.
1. Introduction
Blocking-state operation of modular multilevel converters is unavoidable in HVDC systems, arising during uncontrolled charging when IGBTs lack sufficient startup voltage and during DC fault protection when voltage collapse and current reversal force submodules into blocking. In this mode, energy transfer is governed entirely by diode conduction and extinction within bridge-arm submodules, and diode state is determined jointly by submodule current and diode terminal voltage. Fixed-step electromagnetic transient simulation samples only at discrete time-step boundaries, yet the actual diode switching instant may fall anywhere inside a single step. Failure to capture that instant produces over-shoot and, in severe cases, numerical oscillation. Offline simulators resolve this through interpolation or variable-step schemes—PSCAD/EMTDC embeds diode switching interpolation, and MATLAB/Simulink shrinks the step during switching events—but real-time simulation must maintain strict synchronization between simulation time and physical time, rendering rollback-capable interpolation and variable-step computation intolerable.
Existing real-time remedies remain tethered to small-step conditions. Inductance/capacitance equivalent diode models, widely deployed in RTDS and RTLAB, avoid admittance-matrix switching and improve efficiency but inject virtual energy loss that scales with step size; RC snubber branches across diodes suppress oscillation through artificially added damping whose parameter selection lacks systematic analysis; and RTLAB timestamp-based compensation depends on FPGA high-speed clocks and CPU–FPGA interaction. All these approaches exploit fine-grained temporal resolution, confining them to FPGA platforms with steps of 1–2 μs. At 50 μs on multi-core CPUs, direct prediction—extrapolating the next switching state from the previous step's node voltages—collapses in accuracy because multiple commutations can occur within one step. This work aggregates behaviorally identical blocking-state diodes into a unified equivalent circuit and exploits submodule internal topology and electrical constraints to construct a robust prediction mechanism, validated on the ADPSS platform through both offline and real-time simulation.
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ZHOU Xin, PENG Hongying, MU Qing, HU Shanhua, LI Yalou, ZHOU Xiaoxin (2026). A Blocking-State Prediction Method for MMC Oriented to Large-Step Electromagnetic Transient Real-Time Simulation. Power Automation Equipment. https://doi.org/10.16081/j.epae.202606022
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Frequently Asked Questions
What is the dominant failure mechanism of conventional direct prediction at a 50 μs step, and how does the proposed constraint-based method suppress it?
Direct prediction samples diode terminal voltages at the previous time-step boundary and extrapolates the next switching state. At 50 μs, a diode may undergo multiple natural commutation events within a single step, so the sampled voltage no longer represents the intra-step trajectory; the resulting state misjudgment produces over-shoot and numerical oscillation. The proposed method aggregates behaviorally identical blocking-state diodes into a unified equivalent circuit and applies submodule internal topological and electrical constraints to bound the admissible state set, eliminating the unconstrained extrapolation that permits misjudgment. Empirically, prediction failure rate is significantly lower than direct prediction, and computational error remains within 3‰–7‰ at 50 μs.
Does the constraint-based prediction mechanism fit within the 50 μs real-time budget on a multi-core CPU, and what is the measured margin?
Yes. Per-arm computation tasks are distributed to independent CPU cores under a parallel architecture, and the total computation time for a single simulation step is held to approximately 22.23 μs. Against the 50 μs real-time constraint, this leaves a margin of roughly 27.77 μs, or 55.5% of the step budget. The method requires neither interpolation rollback nor variable-step recomputation, so no hidden latency is introduced beyond the measured 22.23 μs.
How does this approach compare against inductance/capacitance equivalent diode models deployed in RTDS and RTLAB?
Inductance/capacitance equivalent models maintain constant admittance and avoid admittance-matrix switching, but they inject virtual energy loss at each state transition, and the resulting error grows monotonically with step size. Compensation methods improve accuracy yet leave non-negligible error at large steps. The proposed method does not rely on equivalent admittance switching at all; it predicts the blocking state from submodule internal constraints, achieving 3‰–7‰ error at 50 μs without virtual energy loss artifacts. It also avoids the FPGA high-speed clock and CPU–FPGA interaction overhead required by RTLAB timestamp-based compensation.
What is the scalability ceiling when extending this method to large-scale MMC systems with many bridge arms?
Scalability is governed by core count rather than algorithmic complexity. Because blocking-state submodules within an arm are behaviorally identical, they are aggregated into a single equivalent blocking circuit, so per-arm computational load does not grow linearly with submodule count N. Each arm is assigned to an independent CPU core, and the measured 22.23 μs per-step total confirms that the parallel decomposition sustains the 50 μs deadline. The binding constraint is the availability of CPU cores to map additional arms, not the prediction mechanism itself.
Does the method apply to full-bridge submodules, and how does their multi-path conduction affect prediction?
Yes. Full-bridge submodules exhibit two distinct charging paths under blocking: D1/D4 conduction yields positive output voltage, while D2/D3 conduction yields negative output voltage, with D2/D3 and D1/D4 states mutually exclusive. The unified aggregation remains valid because all submodules in an arm carry identical current and operate in identical states, so the arm reduces to a single equivalent blocking circuit regardless of whether half-bridge or full-bridge topology is used. The internal constraint set is extended to cover both conduction path pairs, preserving the 3‰–7‰ error bound at 50 μs.
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