• • At a 50 μs simulation step, the proposed blocking-state prediction method holds computational error within 3‰–7‰, whereas conventional direct prediction suffers severe accuracy degradation once diode states change multiple times within a single step; this threshold is decisive because 50 μs is the practical ceiling for multi-core CPU real-time simulation of large-scale MMC grids.
• • Single-step total computation time is constrained to approximately 22.23 μs on a multi-core CPU parallel architecture with per-arm task allocation to independent cores, leaving a 27.77 μs margin against the 50 μs real-time deadline and confirming that constraint-based prediction does not introduce rollback or interpolation overhead.
• • Prediction failure rate is significantly lower than that of the traditional direct prediction method under identical 50 μs conditions, directly addressing the over-shoot and numerical oscillation mechanisms that arise when natural diode commutation instants fall inside a fixed time step.
• • The method eliminates dependence on FPGA high-speed clock signals and CPU–FPGA timestamp interaction required by RTLAB-style error compensation, and avoids the virtual energy loss inherent to inductance/capacitance equivalent diode models whose error grows monotonically with step size.