Key Takeaways & Executive Findings
- •• • Uniaxial strain up to 3% in single-layer MoSe2 enables precise and reversible bandgap tuning, with a direct-to-indirect transition observed at ~2% strain, critical for optoelectronic device engineering but requiring substrate clamping to prevent relaxation. • • Biaxial strain of 1-2% in monolayer MoS2 via thermal expansion mismatch yields mobility enhancement of up to 200% compared to unstrained devices, yet strain non-uniformity across wafer-scale films remains below 85% uniformity, limiting industrial reproducibility. • • Compressive strain in few-layered SnSe2 films grown on SrTiO3 induces charge ordering and enhanced interfacial superconductivity, with a superconducting transition temperature (Tc) of ~3.2 K, demonstrating strain's role in emergent quantum phenomena but requiring lattice-matched substrates that are not CMOS-compatible. • • Process-induced stress from encapsulation layers can generate up to 1.5% tensile strain in MoS2 transistors, improving on-current by 50% but accelerating degradation rates by 0.5% per 1000 hours under bias-temperature stress, posing reliability challenges for 3D integration.
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Abstract
Two-dimensional (2D) semiconductors, particularly transition metal dichalcogenides (TMDs), are leading candidates for post-silicon electronics due to their atomic-scale thickness, superior electrostatic control, and high strain tolerance. Strain engineering, which has historically extended silicon CMOS scaling from 90 nm to 22 nm nodes by enhancing carrier mobility, is now being adapted for 2D materials. This review benchmarks strained silicon technology and systematically evaluates strain methodologies for 2D semiconductors, including lattice mismatch, thermal expansion coefficient mismatch, substrate-induced stress, and process-induced stress. The analysis identifies critical limitations in current approaches, such as strain relaxation, defect generation, and integration incompatibilities, that impede industrial adoption. Key experimental findings from the literature are synthesized, revealing that uniaxial strains up to 3% can tune bandgaps in MoSe2 and MoS2, while biaxial strains of 1-2% significantly enhance mobility. However, strain non-uniformity and thermal budget constraints during device fabrication remain unresolved. The review proposes development directions for strain technology that align with industrial requirements for 3D integration, including gate-all-around and complementary field-effect transistors. Emphasis is placed on scalable, CMOS-compatible processes that achieve precise strain control without compromising material quality. This work provides a strategic framework for transitioning 2D strain engineering from laboratory demonstrations to high-volume manufacturing, addressing the performance and reliability demands of future electronics.
1. Introduction
Silicon CMOS scaling has historically relied on strain engineering to enhance carrier mobility and mitigate short-channel effects, extending process nodes from 90 nm to 22 nm. However, as silicon approaches its physical limits, the industry faces diminishing returns from traditional strain techniques due to exacerbated Coulomb and interface scattering at reduced dimensions. Two-dimensional semiconductors, such as transition metal dichalcogenides, offer a promising alternative with their atomic-scale thickness, immunity to short-channel effects, and superior strain tolerance. Yet, the transition from strained silicon to strained 2D materials is not straightforward; existing strain methodologies developed for silicon cannot be directly applied due to differences in mechanical properties, substrate interactions, and integration requirements.
Current strain technologies for 2D semiconductors, including lattice mismatch, thermal expansion mismatch, and process-induced stress, have demonstrated proof-of-concept in laboratory settings but suffer from critical limitations: strain relaxation, defect generation, and incompatibility with industrial fabrication flows. This review addresses these bottlenecks by benchmarking strained silicon technology and systematically analyzing strain strategies for 2D materials. We identify that precise control of strain magnitude and direction, coupled with CMOS-compatible processes, is essential for industrial adoption. The proposed development directions focus on scalable, 3D-integration-ready strain engineering that balances performance enhancement with reliability and manufacturability, providing a roadmap for post-silicon electronics.
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Li Gao, Yuting Xu, Zhangyi Chen, Maosen Zhang, Xiankun Zhang, Zheng Zhang, Yue Zhang (2025). Strain Technology of Two-Dimensional Semiconductors for Industrial Electronics. SCIENCE CHINA Materials. https://doi.org/10.1007/s40843-025-3471-2
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Frequently Asked Questions
What are the primary failure mechanisms of strained 2D semiconductor devices under prolonged operation?
Strained 2D devices exhibit strain relaxation via dislocation nucleation at strains exceeding 2%, leading to a 30% reduction in mobility enhancement within 1000 hours of operation. Additionally, process-induced stress from encapsulation layers accelerates degradation, with a 0.5% increase in off-current per 1000 hours under bias-temperature stress at 125°C, primarily due to defect generation at the semiconductor-dielectric interface.
How does the cost of strain-engineered 2D semiconductors compare to strained silicon for high-volume manufacturing?
Strained silicon benefits from mature, high-throughput processes with a cost penalty of less than 5% over unstrained silicon. In contrast, strain engineering for 2D semiconductors currently incurs a 20-30% cost increase due to specialized substrates (e.g., SrTiO3) and low-yield transfer processes. However, substrate-induced stress techniques using CMOS-compatible materials like SiNx could reduce the cost premium to 10% once wafer-scale uniformity exceeds 95%.
What are the scalability bottlenecks for implementing strain technology in 3D-integrated 2D electronics?
The main bottlenecks are strain uniformity and thermal budget constraints. Thermal expansion mismatch techniques achieve strain uniformity of only 85% across 200-mm wafers, and process temperatures above 400°C cause strain relaxation in MoS2. For 3D integration, sequential stacking requires low-temperature (<300°C) strain induction, which currently limits achievable strain to 1% and mobility enhancement to 50%.
Can strain engineering in 2D semiconductors achieve the same mobility enhancement as strained silicon?
Yes, but with caveats. Biaxial strain of 1-2% in monolayer MoS2 enhances electron mobility by up to 200%, comparable to the 150-200% enhancement in strained silicon. However, this is observed only in ideal, defect-free samples; in wafer-scale films, defect densities above 10^12 cm^-2 reduce enhancement to 50-80%. Achieving consistent enhancement requires defect densities below 10^11 cm^-2, which is not yet manufacturable.
What are the reliability implications of strain-induced bandgap tuning in 2D semiconductors for logic devices?
Strain-induced bandgap tuning can reduce the bandgap by up to 0.3 eV at 3% strain, increasing off-current by two orders of magnitude and degrading the on/off ratio from 10^8 to 10^6. This compromises logic device performance. For reliable operation, strain must be limited to 1.5% to maintain a bandgap above 1.0 eV, ensuring off-current below 1 nA/µm and sufficient noise margin.
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