Strain Technology of Two-Dimensional Semiconductors for Industrial Electronics
Two-dimensional (2D) semiconductors, particularly transition metal dichalcogenides (TMDs), are leading candidates for post-silicon electronics due to their atomic-scale thickness, superior electrostatic control, and high strain tolerance. Strain engineering, which has historically extended silicon CMOS scaling from 90 nm to 22 nm nodes by enhancing carrier mobility, is now being adapted for 2D materials. This review benchmarks strained silicon technology and systematically evaluates strain methodologies for 2D semiconductors, including lattice mismatch, thermal expansion coefficient mismatch, substrate-induced stress, and process-induced stress. The analysis identifies critical limitations in current approaches, such as strain relaxation, defect generation, and integration incompatibilities, that impede industrial adoption. Key experimental findings from the literature are synthesized, revealing that uniaxial strains up to 3% can tune bandgaps in MoSe2 and MoS2, while biaxial strains of 1-2% significantly enhance mobility. However, strain non-uniformity and thermal budget constraints during device fabrication remain unresolved. The review proposes development directions for strain technology that align with industrial requirements for 3D integration, including gate-all-around and complementary field-effect transistors. Emphasis is placed on scalable, CMOS-compatible processes that achieve precise strain control without compromising material quality. This work provides a strategic framework for transitioning 2D strain engineering from laboratory demonstrations to high-volume manufacturing, addressing the performance and reliability demands of future electronics.