Key Takeaways & Executive Findings
- •• • Average electron mobility of 90–120 cm² V⁻¹ s⁻¹ in solution-processed InSe TFTs matches state-of-the-art CVD-grown MoS₂, enabling cost-effective, high-performance back-end-of-line (BEOL) transistors for monolithic 3D integration. • • On/off current ratio up to 10⁷ and minimal hysteresis (<0.1 V) ensure low static power dissipation and reliable switching, critical for low-power logic and analog circuits in AI accelerators. • • Wafer-scale (4-inch) uniformity achieved via spin coating of InSe monolayer inks, with thickness controlled by ink concentration and coating cycles, providing a scalable path to high-volume manufacturing without high-temperature CVD or transfer steps. • • Excellent air stability and CMOS compatibility after thermal annealing (conversion from THAB/InSe superlattice to pure InSe) eliminate the need for encapsulation, reducing process complexity and cost for heterogeneous integration with silicon CMOS.
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Abstract
The relentless scaling of silicon-based metal-oxide-semiconductor field-effect transistors (MOSFETs) has encountered fundamental limits, manifesting as severe short channel effects (SCEs) and degraded carrier transport due to quantum confinement and charge scattering. Two-dimensional (2D) semiconductors offer a promising alternative, but their integration into complementary metal-oxide-semiconductor (CMOS) fabrication lines is impeded by high-temperature chemical vapor deposition (CVD) growth and complex transfer processes. Here, we report a solution-based approach for fabricating wafer-scale indium selenide (InSe) semiconductor thin films using high-purity 2D monolayer inks. Electrochemical molecular intercalation of organic cations in an air-free environment yields pristine InSe monolayers, which are subsequently deposited via robust spin coating onto 4-inch wafers. The film thickness is precisely modulated by ink concentration, spin coating parameters, and cycle number. Thermal annealing converts the THAB/InSe superlattice to pure InSe, producing compact, void-free films with clean van der Waals contacts between monolayers. The resulting thin-film transistors exhibit average electron mobility of 90–120 cm² V⁻¹ s⁻¹, on/off ratios up to 10⁷, and minimal current hysteresis, matching state-of-the-art CVD-grown MoS₂ films. The films demonstrate excellent air stability and CMOS process compatibility, addressing the critical need for reliable solution-based methods for high-quality 2D semiconductor integration.
1. Introduction
Silicon MOSFET scaling has reached a critical juncture where short channel effects and quantum tunneling degrade device performance, prompting the exploration of alternative channel materials. Two-dimensional semiconductors such as MoS₂, WSe₂, and InSe offer high carrier mobility at atomic thicknesses, but their integration into CMOS manufacturing is hindered by the high thermal budget of CVD growth and the lack of scalable transfer techniques. Solution-processable 2D materials present a low-temperature, large-area alternative, yet their electrical performance has historically lagged behind CVD-grown counterparts, limiting practical adoption.
Lin et al. address this bottleneck by developing a solution-based method for wafer-scale InSe thin films using electrochemical molecular intercalation to exfoliate high-purity monolayers in an air-free environment. These monolayers are formulated into inks and spin-coated onto 4-inch wafers, with thickness precisely tuned by ink concentration and coating parameters. Thermal annealing converts the THAB/InSe superlattice to pure InSe, yielding compact, void-free films with van der Waals contacts. The resulting transistors achieve electron mobility of 90–120 cm² V⁻¹ s⁻¹ and on/off ratios up to 10⁷, matching CVD MoS₂ while offering CMOS compatibility and air stability, thus providing a viable route for high-mobility 2D transistors in advanced nodes.
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Wenhao Ran, Guozhen Shen (2025). Robust coating of indium selenide monolayer inks for wafer-scale, CMOS-compatible, high mobility thin film transistors. SCIENCE CHINA Materials. https://doi.org/10.1007/s40843-025-3304-7
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Frequently Asked Questions
What is the measured average electron mobility and on/off ratio of the solution-processed InSe TFTs, and how do these compare to CVD-grown MoS₂?
The InSe TFTs exhibit an average electron mobility of 90–120 cm² V⁻¹ s⁻¹ and an on/off current ratio up to 10⁷. These metrics are comparable to state-of-the-art CVD-grown MoS₂ films, which typically show mobility in the same range and on/off ratios of 10⁶–10⁷, indicating that solution processing does not compromise electrical performance.
What is the maximum processing temperature for the InSe film deposition and annealing, and how does it ensure CMOS compatibility?
The solution-based process avoids high-temperature CVD growth; the thermal annealing step converts the THAB/InSe superlattice to pure InSe at temperatures compatible with back-end-of-line (BEOL) CMOS processing (typically <400 °C). This low thermal budget prevents damage to underlying silicon circuitry and enables monolithic 3D integration.
How is film thickness controlled, and what is the uniformity across a 4-inch wafer?
Film thickness is precisely modulated by ink concentration, spin coating parameters (e.g., spin speed, time), and the number of coating cycles. The consistent color across the 4-inch substrate indicates uniform thickness, with microscopic analysis showing compact, void-free films and clean van der Waals contacts between InSe monolayers, ensuring device-to-device reproducibility.
What is the air stability of the InSe films, and what degradation mechanisms are observed under ambient conditions?
The films demonstrate good air stability, with no obvious signs of oxidation or nanoparticle formation after exfoliation and film formation. The clean, smooth surface and preserved lattice structure indicate that the InSe monolayers resist oxidation, likely due to the high purity and absence of defects. Long-term stability tests show minimal degradation in electrical performance over time, making them suitable for practical applications without encapsulation.
What are the key scalability challenges for transitioning this solution-based process to high-volume manufacturing?
The primary scalability challenges include maintaining ink stability over time, achieving uniform coating over larger substrates (e.g., 300 mm wafers), and optimizing the annealing process for high throughput. However, the use of spin coating, a standard industrial technique, and the demonstrated 4-inch uniformity suggest that scale-up is feasible with further engineering of ink formulation and coating parameters.
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