• • Average electron mobility of 90–120 cm² V⁻¹ s⁻¹ in solution-processed InSe TFTs matches state-of-the-art CVD-grown MoS₂, enabling cost-effective, high-performance back-end-of-line (BEOL) transistors for monolithic 3D integration.
• • On/off current ratio up to 10⁷ and minimal hysteresis (<0.1 V) ensure low static power dissipation and reliable switching, critical for low-power logic and analog circuits in AI accelerators.
• • Wafer-scale (4-inch) uniformity achieved via spin coating of InSe monolayer inks, with thickness controlled by ink concentration and coating cycles, providing a scalable path to high-volume manufacturing without high-temperature CVD or transfer steps.
• • Excellent air stability and CMOS compatibility after thermal annealing (conversion from THAB/InSe superlattice to pure InSe) eliminate the need for encapsulation, reducing process complexity and cost for heterogeneous integration with silicon CMOS.