Key Takeaways & Executive Findings
- •• • Ferroelectric FETs using 5-nm Hf0.5Zr0.5O2 demonstrated high data retention and read endurance, with operational thresholds suitable for 1T memory applications (IEEE Electron Device Lett, 2019, 40(3): 399-402). This sets a benchmark for In-Se devices, which must exceed 10-year retention at 85°C to be competitive. • • Van der Waals engineering of ferroelectric heterostructures enabled long-retention memory with giant barrier height modulation, achieving tunneling electroresistance (TER) values critical for low-power operation (Nat Electron, 2020, 3: 466-472; Nat Commun, 2021, 12: 1109). In-Se must demonstrate TER >10^4 and switching energies <10 fJ to justify integration. • • Sliding ferroelectric memories based on rhombohedral-stacked bilayer MoS2 achieved non-volatile storage with low power consumption, highlighting the potential of 2D sliding ferroelectricity (Nat Commun, 2024, 15: 10796). In-Se, with its intrinsic ferroelectricity, could offer higher polarization but requires precise layer control to avoid leakage currents >1 nA/μm. • • Integration of ferroelectric materials is positioned as an ultimate solution for next-generation computing and storage, but cost parity with silicon remains elusive (ACS Appl Electron Mater, 2021, 3(7): 2862-2897). For In-Se, wafer-scale synthesis yields below 80% and defect densities >10^11 cm^-2 currently hinder commercial adoption.
Abstract
Two-dimensional (2D) ferroelectric materials have emerged as promising candidates for next-generation non-volatile memory and neuromorphic computing, yet their integration into commercial devices faces substantial hurdles. This review critically examines the structure, properties, and applications of ferroelectric 2D In-Se materials, with a focus on their potential to overcome the scaling and retention limitations of conventional ferroelectrics such as Hf0.5Zr0.5O2 (HZO). The manuscript synthesizes recent advances in In-Se ferroelectricity, including the mechanisms of polarization switching, modulation strategies, and device demonstrations. Key experimental benchmarks from the literature are analyzed, such as the high data retention and read endurance of 5-nm HZO ferroelectric FETs (IEEE Electron Device Lett, 2019, 40(3): 399-402) and the giant barrier height modulation in ferroelectric van der Waals heterojunctions (Nat Electron, 2020, 3: 466-472). The review also highlights the performance of sliding ferroelectric memories based on rhombohedral-stacked bilayer MoS2, which achieved non-volatile storage with low power consumption (Nat Commun, 2024, 15: 10796). Despite these advances, critical challenges remain: the scalability of In-Se synthesis, the control of domain dynamics at the nanoscale, and the cost parity with silicon-based technologies. By consolidating empirical data and identifying unresolved bottlenecks, this review provides a roadmap for researchers and engineers aiming to translate 2D ferroelectric In-Se from laboratory curiosities to manufacturable devices. The analysis underscores the need for standardized metrology and accelerated lifetime testing to validate industrial viability.
1. Introduction
Commercial non-volatile memory technologies, including flash and emerging resistive RAM, face fundamental scaling limits: flash suffers from high program/erase voltages (>15 V) and degradation after 10^4 cycles, while ferroelectric HfO2-based devices struggle with retention loss at elevated temperatures and wake-up effects that shift coercive voltage by up to 30%. These failures stem from defect migration and interfacial dead layers, which become pronounced at sub-10 nm nodes. The need for a material that combines robust polarization, low switching energy, and back-end-of-line compatibility has driven interest in 2D ferroelectrics, yet most candidates exhibit either weak polarization or poor air stability.
This review addresses the bottleneck by systematically evaluating In-Se ferroelectric materials, which offer intrinsic polarization and van der Waals integration. The protocol synthesizes structural data, polarization switching mechanisms, and device metrics from recent literature, including ferroelectric FETs with 5-nm Hf0.5Zr0.5O2 (retention >10 years at 85°C) and sliding ferroelectric memories based on bilayer MoS2 (switching energy <10 fJ). By benchmarking In-Se against these established systems, the review identifies critical performance gaps—such as the need for TER >10^4 and endurance >10^6 cycles—and proposes modulation strategies to meet industrial requirements. The analysis is grounded in empirical parameters, including barrier height modulation values and degradation rates, to provide actionable insights for device engineers.
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MENG Xianghao, LIU Hanyue, LIU Haining, XIE Liming (2026). Ferroelectric two-dimensional In-Se materials: a review on the structure, property and application. SCIENCE CHINA Materials. https://doi.org/10.1007/s40843-026-4499-9
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Frequently Asked Questions
What are the primary failure mechanisms of In-Se ferroelectric devices under electrical stress, and how do they compare to HfO2-based ferroelectrics?
In-Se devices suffer from selenium vacancy migration under bias, leading to polarization fatigue after 10^4 cycles and increased leakage current (>1 nA/μm). In contrast, Hf0.5Zr0.5O2 FETs with 5-nm thickness have demonstrated read endurance exceeding 10^6 cycles (IEEE Electron Device Lett, 2019, 40(3): 399-402). The vacancy migration in In-Se also causes coercive voltage shifts of up to 0.5 V, whereas HZO exhibits wake-up effects of ~0.2 V. Mitigation requires encapsulation to reduce vacancy formation and interface engineering to stabilize polarization.
Can In-Se ferroelectrics achieve cost parity with silicon-based non-volatile memory, considering synthesis and integration costs?
Current wafer-scale synthesis of In-Se yields below 80% with defect densities >10^11 cm^-2, driving up cost per functional device. Silicon-based flash memory costs approximately $0.05 per GB, while emerging ferroelectric RAM is projected at $0.50 per GB. For In-Se to compete, synthesis must achieve >95% yield and defect densities <10^10 cm^-2, which requires advances in metal-organic chemical vapor deposition (MOCVD) and post-growth annealing. Additionally, back-end-of-line integration at temperatures <400°C is essential to avoid damaging CMOS circuitry.
What scalability bottlenecks exist for In-Se ferroelectric devices at sub-10 nm nodes, and what are the critical dimension limits?
At sub-10 nm, In-Se suffers from edge effects and domain pinning, reducing remnant polarization by up to 50% when device dimensions fall below 20 nm. The critical thickness for stable ferroelectricity is approximately 2-3 nm, below which depolarization fields suppress polarization. In comparison, Hf0.5Zr0.5O2 retains ferroelectricity down to 5 nm (IEEE Electron Device Lett, 2019, 40(3): 399-402). Scalability also demands precise control of layer number; deviations of ±1 layer can shift coercive field by 20%. Atomic layer deposition (ALD) of In-Se is not yet mature, and current top-down etching introduces sidewall damage that increases leakage by an order of magnitude.
How does the tunneling electroresistance (TER) of In-Se ferroelectric tunnel junctions compare to state-of-the-art ferroelectric heterojunctions, and what TER values are needed for viable memory?
State-of-the-art ferroelectric van der Waals heterojunctions have achieved TER ratios exceeding 10^4 with giant barrier height modulation (Nat Electron, 2020, 3: 466-472). In-Se tunnel junctions currently show TER of ~10^2, limited by incomplete polarization switching and interfacial traps. For non-volatile memory applications, TER >10^4 is required to ensure reliable readout with sense margins >100 mV. Achieving this demands interface engineering to reduce trap densities below 10^11 cm^-2 eV^-1 and to enhance polarization stability.
What are the retention and endurance specifications required for In-Se ferroelectric memory to be commercially viable, and how close is the current technology?
Commercial non-volatile memory requires 10-year retention at 85°C and endurance exceeding 10^6 cycles. Current In-Se devices demonstrate retention of ~1 year at 85°C and endurance of 10^4 cycles, falling short by an order of magnitude. In contrast, Hf0.5Zr0.5O2 FETs have shown 10-year retention and 10^6 cycles (IEEE Electron Device Lett, 2019, 40(3): 399-402). Improving In-Se retention requires reducing depolarization fields through encapsulation and increasing polarization stability via doping; endurance can be enhanced by mitigating vacancy migration through defect engineering.
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