Key Takeaways & Executive Findings
- •• • In-situ oxidation of Bi2O2Se at temperatures below 400°C yields wafer-scale α-Bi2SeO5, a van der Waals ferroelectric oxide with robust ferroelectricity down to the monolayer limit, enabling low-voltage operation below 1 V. • • The α-Bi2SeO5 dielectric exhibits a relative permittivity of ~24 and a Curie temperature of ~880 K, ensuring thermal stability and high capacitive coupling for scaled devices. • • The native ferroelectric buffer eliminates parasitic interlayers and trap states at the interface, mitigating threshold drift and fatigue, thereby enhancing endurance and retention in 2D FeFETs. • • Precise regulation of the oxidation layer thickness allows uniform and controllable ferroelectric gate stacks, addressing the nucleation challenge on dangling-bond-free 2D surfaces and facilitating monolithic 3D integration.
Abstract
The escalating demand for energy-efficient edge inference in artificial intelligence has intensified the search for hardware that transcends the von Neumann bottleneck. Ferroelectric field-effect transistors (FeFETs) are promising due to their non-destructive readout, low programming energy, and multilevel operation. However, integrating ultrathin ferroelectrics with two-dimensional (2D) channels remains challenging due to the inert surfaces of 2D materials, which impede uniform film growth. Moreover, conventional ferroelectrics like doped hafnia and AlScN suffer performance degradation at thicknesses required for sub-1V operation. The interface between ferroelectric and 2D semiconductor is often plagued by traps and parasitic layers, causing threshold drift and fatigue. In a recent Science report, Hailin Peng and colleagues present an innovative solution: a native ferroelectric buffer derived from the semiconductor itself. By oxidizing layered Bi2O2Se below 400°C, they produce wafer-scale α-Bi2SeO5, a van der Waals ferroelectric oxide. This material retains robust ferroelectricity down to the monolayer limit, supporting both out-of-plane and in-plane polarization switching. It exhibits a high relative dielectric constant (~24) and a Curie temperature near 880 K. The in-situ oxidation approach enables precise thickness control, yielding a uniform, switchable, and robust gate stack for 2D FeFETs, addressing the critical challenges of voltage scaling and interface quality.
1. Introduction
The von Neumann architecture, with its physical separation of memory and logic, imposes severe latency and power penalties due to constant data movement. This bottleneck is particularly acute for edge AI inference, which demands energy-efficient, low-voltage operation. Ferroelectric field-effect transistors (FeFETs) offer a compelling alternative by combining nonvolatile storage with in-memory computation. However, conventional FeFETs based on hafnia or AlScN face fundamental limitations: as ferroelectric thickness is reduced to achieve sub-1V switching, polarization stability and reliability degrade. Furthermore, integrating these materials with 2D semiconductors is hindered by the inert, dangling-bond-free surfaces of 2D materials, which impede uniform film nucleation. The resulting interfaces are often defective, leading to charge trapping, threshold drift, and fatigue.
To overcome these obstacles, a paradigm shift is required: instead of depositing a ferroelectric onto the 2D channel, the ferroelectric should be derived from the channel material itself. Peng and colleagues demonstrate this by oxidizing layered Bi2O2Se at temperatures below 400°C to form α-Bi2SeO5, a van der Waals ferroelectric oxide. This in-situ approach yields a native, atomically sharp interface, eliminating parasitic layers and trap states. The resulting ferroelectric retains robust polarization down to the monolayer limit, with a high dielectric constant (~24) and exceptional thermal stability (Curie temperature ~880 K). This innovation directly addresses the voltage scaling and interface quality bottlenecks, paving the way for reliable, low-voltage 2D FeFETs suitable for energy-efficient edge computing.
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Chao Zhou, Zhihao Yu, Xinran Wang (2026). An In-Situ Oxidation Routine for Reliable Low-Voltage 2D FeFETs. SCIENCE CHINA Materials. https://doi.org/10.1007/s40843-026-4215-3
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Frequently Asked Questions
What is the maximum operating temperature for the in-situ formed α-Bi2SeO5 ferroelectric, and how does it compare to conventional ferroelectrics like HfO2?
The Curie temperature of α-Bi2SeO5 is approximately 880 K (about 607°C), which is significantly higher than that of doped HfO2 (typically around 450-500°C). This high thermal stability ensures that the ferroelectric properties remain robust under elevated temperatures, making it suitable for applications requiring high-temperature operation or back-end-of-line integration.
How does the in-situ oxidation process ensure uniformity and thickness control at the wafer scale?
The oxidation of Bi2O2Se is performed at temperatures below 400°C, which allows precise regulation of the oxide layer thickness by controlling the oxidation time and temperature. The process yields wafer-scale uniformity, as demonstrated by the production of α-Bi2SeO5 films with consistent ferroelectric properties across the wafer. This precision is critical for manufacturing reliable devices with predictable performance.
What are the endurance and retention characteristics of the 2D FeFETs fabricated using this in-situ oxidation approach?
While the abstract does not provide specific endurance and retention numbers, the elimination of parasitic interlayers and trap states at the ferroelectric/2D interface is expected to significantly improve cycling endurance and data retention. The robust ferroelectricity down to the monolayer limit and the high Curie temperature suggest that the devices can withstand repeated switching without significant fatigue, making them suitable for nonvolatile memory applications.
How does the dielectric constant of α-Bi2SeO5 (~24) impact the device performance compared to other high-κ dielectrics?
A high dielectric constant of ~24 allows for a larger capacitance density, which is beneficial for achieving lower operating voltages and better electrostatic control in scaled transistors. This is particularly important for low-voltage FeFETs, as it enables a larger voltage drop across the ferroelectric layer, facilitating polarization switching at lower applied voltages. Compared to SiO2 (κ=3.9) or even HfO2 (κ~20-25), α-Bi2SeO5 offers competitive performance while also providing ferroelectric functionality.
What are the potential challenges for integrating this in-situ oxidation process into existing CMOS fabrication flows?
The oxidation temperature below 400°C is compatible with back-end-of-line (BEOL) processing, which is crucial for monolithic 3D integration. However, the process must be carefully controlled to avoid oxidation of underlying layers or devices. Additionally, the growth of Bi2O2Se and its subsequent oxidation may require specialized equipment and handling, but the wafer-scale uniformity and low thermal budget make it a promising candidate for industrial adoption.
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