An In-Situ Oxidation Routine for Reliable Low-Voltage 2D FeFETs
The escalating demand for energy-efficient edge inference in artificial intelligence has intensified the search for hardware that transcends the von Neumann bottleneck. Ferroelectric field-effect transistors (FeFETs) are promising due to their non-destructive readout, low programming energy, and multilevel operation. However, integrating ultrathin ferroelectrics with two-dimensional (2D) channels remains challenging due to the inert surfaces of 2D materials, which impede uniform film growth. Moreover, conventional ferroelectrics like doped hafnia and AlScN suffer performance degradation at thicknesses required for sub-1V operation. The interface between ferroelectric and 2D semiconductor is often plagued by traps and parasitic layers, causing threshold drift and fatigue. In a recent Science report, Hailin Peng and colleagues present an innovative solution: a native ferroelectric buffer derived from the semiconductor itself. By oxidizing layered Bi2O2Se below 400°C, they produce wafer-scale α-Bi2SeO5, a van der Waals ferroelectric oxide. This material retains robust ferroelectricity down to the monolayer limit, supporting both out-of-plane and in-plane polarization switching. It exhibits a high relative dielectric constant (~24) and a Curie temperature near 880 K. The in-situ oxidation approach enables precise thickness control, yielding a uniform, switchable, and robust gate stack for 2D FeFETs, addressing the critical challenges of voltage scaling and interface quality.