Key Takeaways & Executive Findings
- •• • The ACIM array consumes 98.7% of total energy during 256 × 256 floating-point matrix multiplication, while the DDFP processor consumes only 1.3%, indicating that energy efficiency is dominated by the analogue domain and that digital overhead is minimal, which is critical for edge deployment where power budgets are constrained. • • The quantization unit converts floating-point feature maps to INT-8 with FP-15 scaling factors, and the dequantization unit recovers FP-32 outputs, enabling high-precision regression tasks that were previously infeasible with pure ACIM systems that rely on low-precision integer computations. • • The hybrid mapper distributes matrix multiplication across analogue and digital domains with single row and column granularity, improving array spatial utilization and floating-point compatibility, which directly addresses the limited dynamic range and noise accumulation issues that hinder ACIM in object detection and other complex regression applications. • • The prototype integrates up to 12 memristor arrays and an RISC-V softcore CPU on a Xilinx FPGA, demonstrating a scalable and reconfigurable hardware platform that bridges analogue and digital domains, facilitating seamless deployment of neural networks with mixed precision requirements.
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Abstract
Analogue compute-in-memory (ACIM) systems leveraging memristor crossbar arrays offer exceptional energy efficiency and parallelism for neural network classification tasks but face critical limitations in regression tasks requiring high dynamic range and floating-point precision. The reliance on low-precision integer computations and susceptibility to noise accumulation restrict their applicability to complex regression problems such as object detection. This work presents the memristor-based AnDi architecture, a dual-domain system integrating ACIM arrays with digital cores to overcome these limitations. The architecture incorporates a dual-domain floating-point processor (DDFP) that enables seamless data conversion between analogue and digital domains. A quantization unit transforms floating-point feature maps into 8-bit integer (INT-8) representations with 15-bit floating-point (FP-15) scaling factors, while a dequantization unit recovers high-precision FP-32 outputs. Experimental validation demonstrates that during 256 × 256 floating-point matrix multiplication, the ACIM array consumes 98.7% of total energy, whereas the DDFP processor accounts for only 1.3%, achieving significant energy efficiency. The hybrid mapper flexibly distributes matrix multiplication across both domains with single row and column granularity, enhancing floating-point compatibility, accuracy, and array spatial utilization compared to pure ACIM systems. This dual-domain approach addresses the fundamental bottlenecks of traditional ACIM in floating-point compatibility, noise accumulation, and array utilization, enabling high-precision regression tasks while maintaining energy efficiency. The system integrates up to 12 memristor arrays and an RISC-V softcore CPU on a Xilinx FPGA, demonstrating a viable path for deploying advanced neural network applications in edge computing environments.
1. Introduction
Traditional analogue compute-in-memory (ACIM) systems based on memristor crossbar arrays have demonstrated remarkable energy efficiency and parallelism for neural network classification tasks, yet their application to regression tasks requiring high dynamic range and floating-point precision remains severely constrained. The fundamental limitation arises from ACIM's reliance on low-precision integer computations with constrained dynamic range, which introduces significant noise accumulation and limits floating-point compatibility. These shortcomings render ACIM unsuitable for complex regression tasks such as object detection, where high accuracy and dynamic range are paramount. Consequently, the performance of ACIM systems in such tasks has not been fully validated, and their deployment in real-world edge computing scenarios is hindered by these intrinsic bottlenecks.
To address these challenges, the memristor-based AnDi architecture introduces a dual-domain system that integrates ACIM arrays with digital cores, enabling seamless conversion between analogue and digital domains. The architecture incorporates a dual-domain floating-point processor (DDFP) that quantizes floating-point feature maps into INT-8 representations with FP-15 scaling factors, and subsequently dequantizes to recover FP-32 outputs. This approach overcomes the limitations of pure ACIM by distributing matrix multiplication across both domains with single row and column granularity, thereby enhancing floating-point compatibility, accuracy, and array spatial utilization. Experimental results demonstrate that during 256 × 256 floating-point matrix multiplication, the ACIM array consumes 98.7% of total energy, while the DDFP processor consumes only 1.3%, achieving a favorable energy balance. The prototype, integrating up to 12 memristor arrays and an RISC-V softcore CPU on a Xilinx FPGA, provides a viable path for deploying high-precision neural network applications in edge environments.
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Shixiong Liu, Tao Sun, Yang Li (2025). A Memristor-Based Dual-Domain System for Overcoming Limitations of Traditional Analogue Compute-in-Memory. SCIENCE CHINA Materials. https://doi.org/10.1007/s40843-025-3342-5
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Frequently Asked Questions
What is the energy consumption breakdown between the ACIM array and the DDFP processor during 256 × 256 floating-point matrix multiplication?
The ACIM array consumes 98.7% of the total energy, while the DDFP processor consumes only 1.3%. This indicates that the analogue domain dominates energy usage, but the digital overhead is minimal, ensuring that the overall system remains energy-efficient for edge deployment.
How does the AnDi architecture achieve floating-point compatibility and overcome noise accumulation in ACIM systems?
The architecture employs a dual-domain floating-point processor (DDFP) that quantizes floating-point feature maps into INT-8 with FP-15 scaling factors, and a dequantization unit that recovers FP-32 outputs. This seamless conversion between analogue and digital domains mitigates noise accumulation and enables high-precision regression tasks that are infeasible with pure ACIM.
What is the granularity of matrix multiplication distribution in the hybrid mapper, and how does it improve array spatial utilization?
The hybrid mapper distributes matrix multiplication across analogue and digital domains with single row and column granularity. This fine-grained allocation enhances array spatial utilization by dynamically assigning computations based on task requirements, thereby improving floating-point compatibility and accuracy compared to pure ACIM systems.
What are the scalability limits of the prototype, and how many memristor arrays can be integrated?
The prototype integrates up to 12 memristor arrays and an RISC-V softcore CPU on a Xilinx FPGA. This configuration demonstrates a scalable platform, but further scaling may be constrained by FPGA resource availability and memristor array uniformity, which are critical for industrial deployment.
What are the failure mechanisms under stress for the memristor arrays in this dual-domain system?
The research text does not provide specific failure mechanisms under stress. However, memristor arrays are known to suffer from resistance drift, endurance degradation, and variability, which can affect long-term reliability. The AnDi architecture's digital-assisted calibration may mitigate some of these effects, but further empirical stress testing is required to quantify degradation rates.
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