Key Takeaways & Executive Findings
- •• • Equivalent oxide thickness (EOT) below 0.5 nm achieved via lattice-matched Bi2SeO5 (k = 21) on Bi2O2Se, enabling aggressive gate stack scaling without leakage penalties; this directly addresses the high-k integration bottleneck that has stalled 2D GAAFET commercialization. • • Subthreshold swing (SS) of ~62 mV dec-1 sustained over more than five orders of magnitude of drain current, approaching the room-temperature Boltzmann limit of 60 mV dec-1; such steep switching is essential for low-power logic, reducing static power dissipation in high-density M3D stacks. • • Electron mobility exceeding 280 cm2 V-1 s-1 in a fully encapsulated GAA architecture, outperforming typical CVD-grown monolayer MoS2 channels (often <100 cm2 V-1 s-1); this mobility advantage translates to higher drive current and faster switching speeds at scaled supply voltages. • • Stable operation at 0.5 V with on-current exceeding 1 mA μm-1, demonstrating sufficient drive strength for sub-1V logic; this low-voltage operation is critical for monolithic 3D integration where thermal budget constraints limit power density to <1 W mm-2 per tier.
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Abstract
The relentless scaling of silicon transistors below 5 nm gate lengths has exposed fundamental limits: dangling-bond-induced interface scattering exacerbates short-channel effects, including direct source-drain tunneling and drain-induced barrier lowering, degrading power consumption, signal integrity, and reliability. Gate-all-around field-effect transistors (GAAFETs) mitigate these effects by fully enclosing the channel, but silicon's surface chemistry remains problematic. Two-dimensional (2D) semiconductors offer dangling-bond-free surfaces, atomic-level thickness uniformity, and high electron mobility, enabling sub-1-nm gate lengths without short-channel effects. Their van der Waals layered structure further permits monolithic 3D (M3D) integration for high-density, low-power circuits. Despite theoretical promise, 2D GAA devices face critical bottlenecks in source-drain contacts, gate dielectrics, and interface engineering. The deposition of high-quality, atomically uniform, low-trap-density high-k dielectrics on 2D surfaces is particularly challenging. Tang et al. addressed this by forming layered oxide Bi2SeO5 (k = 21) on Bi2O2Se via ultraviolet-assisted intercalative oxidation, creating an atomically smooth, lattice-matched van der Waals interface. The resulting fully encapsulated 2D Bi2O2Se/Bi2SeO5 GAA heterostructure enabled GAAFETs with equivalent oxide thickness below 0.5 nm, subthreshold swing of ~62 mV dec-1 over five orders of magnitude, electron mobility exceeding 280 cm2 V-1 s-1, and stable operation at 0.5 V with on-current exceeding 1 mA μm-1. These metrics demonstrate superior electrostatic control compared to silicon and other 2D GAAFETs, providing a viable route to M3D circuits beyond silicon.
1. Introduction
Silicon transistor scaling has reached a critical juncture: below 5 nm gate lengths, dangling bonds at the channel surface induce severe interface scattering, exacerbating short-channel effects such as direct source-drain tunneling and drain-induced barrier lowering. These phenomena degrade power consumption, signal integrity, and reliability, effectively capping further density gains in conventional planar MOSFETs and even in early GAAFET architectures. The transition to gate-all-around geometries improves electrostatic control but does not eliminate silicon's intrinsic surface chemistry limitations. Consequently, the semiconductor industry faces a stalled trajectory for sub-5 nm nodes, with diminishing returns on performance and escalating fabrication complexity.
Two-dimensional (2D) semiconductors present a materials-level solution: their dangling-bond-free surfaces, atomic-level thickness uniformity, and high electron mobility enable excellent charge transport even at gate lengths below 1 nm. The van der Waals layered structure further permits monolithic 3D (M3D) integration, stacking high-density device tiers to increase computational density while reducing data-transmission power. However, practical 2D GAAFETs have been hindered by source-drain contacts, gate dielectrics, and interface engineering—particularly the deposition of high-quality, atomically uniform, low-trap-density high-k dielectrics on 2D surfaces. Tang et al. overcome this by forming layered Bi2SeO5 (k = 21) directly on Bi2O2Se via ultraviolet-assisted intercalative oxidation, creating an atomically smooth, lattice-matched van der Waals interface. Their fully encapsulated 2D Bi2O2Se/Bi2SeO5 GAA heterostructure yields EOT < 0.5 nm, SS ~62 mV dec-1 over five orders of magnitude, mobility >280 cm2 V-1 s-1, and stable 0.5 V operation with on-current >1 mA μm-1, establishing a credible path toward M3D circuits beyond silicon.
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FENG Shun, SUN Dong-Ming, CHENG Hui-Ming (2025). 2D Gate-All-Around Logic Devices: A Path Toward Monolithic 3D Circuits Beyond Silicon. SCIENCE CHINA Materials. https://doi.org/10.1007/s40843-025-3352-6
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Frequently Asked Questions
What is the measured subthreshold swing (SS) and over what current range is it maintained?
The device exhibits a steep SS of approximately 62 mV dec-1 over a drain current range spanning more than five orders of magnitude. This near-ideal switching behavior minimizes off-state leakage and enables low-voltage operation, directly addressing the power consumption bottleneck in high-density logic.
How does the electron mobility of this 2D GAAFET compare to typical CVD-grown monolayer MoS2 channels?
The Bi2O2Se/Bi2SeO5 heterostructure achieves electron mobility exceeding 280 cm2 V-1 s-1, whereas CVD monolayer MoS2 GAAFETs typically report mobilities below 100 cm2 V-1 s-1. This >2.8× improvement translates to higher drive current and faster switching at scaled supply voltages.
What is the equivalent oxide thickness (EOT) and dielectric constant of the gate stack?
The gate stack uses layered Bi2SeO5 with a dielectric constant (k) of 21, yielding an EOT below 0.5 nm. This combination provides strong electrostatic control while maintaining low leakage, essential for sub-1V operation and M3D thermal budget constraints.
What on-current is achieved at low operating voltage, and why does this matter for monolithic 3D integration?
The device delivers an on-current exceeding 1 mA μm-1 at a low operating voltage of 0.5 V. This high drive strength at reduced voltage is critical for M3D stacks, where power density per tier must remain below ~1 W mm-2 to avoid thermal degradation of underlying device layers.
What are the remaining barriers to large-scale manufacturing of 2D GAAFETs based on this heterostructure?
Key barriers include scalable synthesis of uniform Bi2O2Se films, precise control of the ultraviolet-assisted intercalative oxidation process for Bi2SeO5 formation, and integration of low-resistance source-drain contacts. While the demonstrated EOT < 0.5 nm and SS ~62 mV dec-1 validate the gate stack, wafer-scale uniformity and defect density control remain unproven, with trap densities likely needing to stay below 1×10^12 cm-2 eV-1 for reliable high-volume manufacturing.
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