2D Gate-All-Around Logic Devices: A Path Toward Monolithic 3D Circuits Beyond Silicon
The relentless scaling of silicon transistors below 5 nm gate lengths has exposed fundamental limits: dangling-bond-induced interface scattering exacerbates short-channel effects, including direct source-drain tunneling and drain-induced barrier lowering, degrading power consumption, signal integrity, and reliability. Gate-all-around field-effect transistors (GAAFETs) mitigate these effects by fully enclosing the channel, but silicon's surface chemistry remains problematic. Two-dimensional (2D) semiconductors offer dangling-bond-free surfaces, atomic-level thickness uniformity, and high electron mobility, enabling sub-1-nm gate lengths without short-channel effects. Their van der Waals layered structure further permits monolithic 3D (M3D) integration for high-density, low-power circuits. Despite theoretical promise, 2D GAA devices face critical bottlenecks in source-drain contacts, gate dielectrics, and interface engineering. The deposition of high-quality, atomically uniform, low-trap-density high-k dielectrics on 2D surfaces is particularly challenging. Tang et al. addressed this by forming layered oxide Bi2SeO5 (k = 21) on Bi2O2Se via ultraviolet-assisted intercalative oxidation, creating an atomically smooth, lattice-matched van der Waals interface. The resulting fully encapsulated 2D Bi2O2Se/Bi2SeO5 GAA heterostructure enabled GAAFETs with equivalent oxide thickness below 0.5 nm, subthreshold swing of ~62 mV dec-1 over five orders of magnitude, electron mobility exceeding 280 cm2 V-1 s-1, and stable operation at 0.5 V with on-current exceeding 1 mA μm-1. These metrics demonstrate superior electrostatic control compared to silicon and other 2D GAAFETs, providing a viable route to M3D circuits beyond silicon.