• • Equivalent oxide thickness (EOT) below 0.5 nm achieved via lattice-matched Bi2SeO5 (k = 21) on Bi2O2Se, enabling aggressive gate stack scaling without leakage penalties; this directly addresses the high-k integration bottleneck that has stalled 2D GAAFET commercialization.
• • Subthreshold swing (SS) of ~62 mV dec-1 sustained over more than five orders of magnitude of drain current, approaching the room-temperature Boltzmann limit of 60 mV dec-1; such steep switching is essential for low-power logic, reducing static power dissipation in high-density M3D stacks.
• • Electron mobility exceeding 280 cm2 V-1 s-1 in a fully encapsulated GAA architecture, outperforming typical CVD-grown monolayer MoS2 channels (often <100 cm2 V-1 s-1); this mobility advantage translates to higher drive current and faster switching speeds at scaled supply voltages.
• • Stable operation at 0.5 V with on-current exceeding 1 mA μm-1, demonstrating sufficient drive strength for sub-1V logic; this low-voltage operation is critical for monolithic 3D integration where thermal budget constraints limit power density to <1 W mm-2 per tier.