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Prof. Liang Chu

School of Materials Science and Engineering, Nanjing University of Science and Technology

Co-Affiliations:School of Materials Science and Engineering, State Key Laboratory of Silicon and Advanced Semiconductor Materials, Zhejiang University

Research Publications & English Decoded Briefs

Showing 2 publications
SCIENCE CHINA Materials2026DOI: 10.1007/s40843-025-3552-2

AB Epoxy Encapsulation-Induced Transparency in Perovskite Films for Light-Emitting Diode Applications

Perovskite light-emitting diodes (PeLEDs) are a promising display technology due to high color purity and solution processability, but their operational stability is compromised by environmental degradation. Encapsulation is essential for practical deployment. Here, we report that applying a commercial AB epoxy adhesive as a cover encapsulant induces a striking transparency transition in Cs0.3MA0.7PbBr3 perovskite films, from yellow to optically clear. The effect is attributed to the alkaline hardener (component B, pH 9–10), which engages in Lewis acid-base coordination with Pb2+ and reacts with Br−, as evidenced by Fourier-transform infrared spectroscopy (redshift of C–O–C stretch from 1035.56 to 1018.05 cm−1, Δν ≈ 17.5 cm−1) and X-ray photoelectron spectroscopy (Pb 4f shift of 0.25 eV, Br 3d5/2 shift of 0.45 eV). This chemical interaction refines perovskite grains to tens of nanometers, shifting light scattering from Mie to Rayleigh regime and enhancing transmittance. Encapsulated devices achieve a maximum luminance of 12,643 cd/m2, a low operational current density, and an increased breakdown voltage of 27 V. The work establishes a framework for selecting encapsulation materials that impart transparency, enabling applications in transparent displays, smart windows, and augmented reality.

SCIENCE CHINA Materials2026DOI: 10.1007/s40843-026-4023-8

Oxide-channel ferroelectric transistor enables ultralow-power NAND flash technology

The escalating power consumption of 3D NAND flash memory, driven by the need for high pass voltages (V_pass) to read cells in vertically stacked strings, poses a critical challenge as layer counts approach 1000. Conventional charge-trap NAND requires V_pass of 5–10 V for quad-level cell (QLC) operation, while silicon-channel ferroelectric NAND suffers from limited memory windows due to low-k interlayers. Here, we highlight a breakthrough by Yoo et al. that introduces an oxide semiconductor (OS)-channel ferroelectric field-effect transistor (FeFET) with a gate stack comprising a zirconium-doped hafnium oxide (HZO) ferroelectric layer sandwiched between low-k (SiO2/SiNx) and high-k (Ta2O5) interlayers, and an indium gallium zinc oxide (IGZO) channel. The absence of hole carriers in IGZO suppresses the 'down' polarization state, enabling a near-zero threshold voltage (V_th) and reducing V_pass to as low as 1 V. The high-k Ta2O5 interlayer prevents oxygen diffusion, mitigating off-current degradation, while the low-k SiO2/SiNx interlayer enhances charge trapping, yielding a memory window exceeding 11 V for a 5-nm SiO2 layer. This enables 5-bit-per-cell (penta-level cell, PLC) operation, surpassing current QLC NAND. The combination of ultralow V_pass and wide memory window achieves both low power consumption and high storage density, positioning OS-channel FeFETs as a promising solution for next-generation memory systems.