• • OS-channel FeFET achieves V_pass as low as 1 V, compared to 5–10 V for conventional QLC NAND, reducing string-level power consumption by over 80% in read/write operations.
• • The memory window exceeds 11 V with a 5-nm-thick SiO2 interlayer, enabling 5-bit-per-cell (PLC) operation, a 25% increase in storage density over current 4-bit QLC NAND.
• • The high-k Ta2O5 interlayer acts as an oxygen diffusion barrier, preventing interfacial defects and off-current degradation, addressing a critical reliability issue in prior OS-based FeFETs.
• • The near-zero V_th, achieved by suppressing the 'down' polarization state in the IGZO channel, eliminates the need for high V_pass to activate unselected cells, directly tackling the power bottleneck in 3D NAND scaling.