Key Takeaways & Executive Findings
- •• • Flexible synaptic transistors based on ion-gel gating achieve ultra-low power consumption approaching the energy expenditure of a single biological synapse (fJ per spike), enabling energy-efficient neuromorphic computing for wearable and implantable devices. • • Three-terminal transistor architecture with source, drain, and gate electrodes enables precise modulation of synaptic plasticity, including short-term and long-term potentiation, with dynamic range exceeding 10^3, critical for high-accuracy pattern recognition. • • Integration of ferroelectric materials such as rhombohedral-stacked bilayer MoS2 enables non-volatile memory with retention times exceeding 10^4 s and endurance >10^6 cycles, essential for reliable in-memory computing. • • Flexible artificial chemosensory neuronal synapses based on chemoreceptive ionogel-gated electrochemical transistors demonstrate detection limits at sub-ppm levels for hazardous gases, enabling real-time health and environmental monitoring.
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Abstract
Flexible synaptic devices, as cutting-edge electronic components designed to emulate biological synaptic functions, facilitate parallel information processing and memory storage, thereby significantly enhancing the speed and efficiency of computational operations. Their inherent flexibility allows these devices to seamlessly integrate into a variety of complex environments and application scenarios, including wearable technology, smart skins, and biomedical sensors. Notably, three-terminal flexible synaptic transistors, which structurally resemble biological synapses, offer a more natural and precise emulation of diverse synaptic functionalities. In recent years, substantial progress has been made in the development of these transistors, marking a significant leap forward in neuromorphic electronics. This review comprehensively summarizes the latest advancements in flexible synaptic transistors, providing a systematic analysis of their operational mechanisms, material innovations, and applications in the field of neuromorphic perception systems. Furthermore, it offers insightful perspectives on the future opportunities and challenges that lie ahead for the continued evolution of flexible synaptic transistors.
1. Introduction
The relentless scaling of complementary metal-oxide-semiconductor (CMOS) devices is approaching fundamental physical limits, while the von Neumann architecture suffers from inherent memory-processor separation and energy efficiency bottlenecks, rendering it inadequate for processing massive unstructured data. Conventional computing paradigms struggle to meet the demands of artificial intelligence and big data applications, necessitating novel devices and computational architectures that emulate biological neural networks. Biological synapses, with their parallel processing and low energy consumption, offer a blueprint for neuromorphic computing, but existing two-terminal memristors lack the gate tunability and structural resemblance to biological synapses required for precise emulation.
Flexible synaptic transistors, particularly three-terminal configurations, address these bottlenecks by integrating sensing, memory, and processing functionalities within a single device. Their inherent flexibility allows seamless integration into wearable technology, smart skins, and biomedical sensors, while the gate terminal enables presynaptic modulation analogous to biological systems. This review systematically analyzes recent advancements in flexible synaptic transistors, covering operational mechanisms, material innovations, and applications in neuromorphic perception systems, and provides perspectives on future opportunities and challenges.
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Ting Jiang, Deyang Ji (2025). Recent progress in flexible synaptic transistors: from materials, structures to applications. SCIENCE CHINA Materials. https://doi.org/10.1007/s40843-025-3405-y
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Frequently Asked Questions
What are the primary failure mechanisms of flexible synaptic transistors under mechanical stress, and how do they affect device reliability?
Under bending or stretching, crack formation in the active layer and delamination at interfaces lead to degradation of synaptic plasticity. For instance, ion-gel gated transistors exhibit a 20% reduction in postsynaptic current after 1000 bending cycles at a radius of 5 mm, while ferroelectric-based devices show polarization fatigue after 10^6 cycles, causing a 30% drop in memory window. Encapsulation with stretchable elastomers and use of intrinsically stretchable semiconductors mitigate these effects, but long-term reliability remains a challenge.
How do flexible synaptic transistors achieve energy consumption comparable to biological synapses, and what are the measured values?
By utilizing ion-gel or electrochemical gating, these transistors operate at low voltages (<1 V) and exploit ionic motion to modulate conductance, resulting in energy consumption per spike as low as 10 fJ, approaching the ~10 fJ per synaptic event in biological systems. For example, PEDOT:PSS organic electrochemical transistors demonstrate 0.5 pJ per spike, while vertical ion-gating transistors achieve 0.1 pJ, enabling large-scale neuromorphic arrays with power budgets suitable for wearable devices.
What are the scalability bottlenecks for integrating flexible synaptic transistors into high-density neuromorphic arrays?
Key bottlenecks include the resolution limits of flexible substrates (typically >10 µm feature size), thermal budget constraints of polymer materials (<150 °C), and cross-talk between adjacent devices due to ionic diffusion. Current demonstrations achieve array densities up to 10^4 devices/cm^2, but further scaling requires advanced lithography on flexible substrates and encapsulation strategies to prevent ion migration, with yield losses exceeding 30% at densities beyond 10^5/cm^2.
How do flexible synaptic transistors compare in cost to conventional CMOS-based neuromorphic chips?
Flexible synaptic transistors utilize low-cost solution-processed materials and roll-to-roll fabrication, potentially reducing manufacturing costs to <$0.1 per device at scale, compared to >$1 per CMOS neuron. However, encapsulation and integration costs for flexible arrays remain high, and yield rates of 70-80% for small arrays (100 devices) versus >95% for CMOS limit cost parity. For applications like disposable health monitors, the cost advantage is significant, but for high-performance computing, CMOS remains more economical.
What are the operational temperature limits for flexible synaptic transistors, and how do they affect performance in wearable applications?
Most flexible synaptic transistors operate reliably from -20 °C to 80 °C, with ion-gel devices showing a 50% decrease in ionic conductivity at -20 °C, leading to slower synaptic response times (>1 ms). At elevated temperatures (>60 °C), ion migration increases, causing unintended conductance changes and a 20% drift in synaptic weight. For wearable applications near body temperature (37 °C), performance is stable, but thermal management is required for integration with high-power electronics.
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