DC Bus Voltage Oscillation Analysis and Impedance Optimization Design for Two-Stage Power Conversion Systems

• • Forward power flow causes the VSC input impedance to exhibit negative impedance characteristics, leading to cascaded system instability and bus voltage oscillations at rated power (800 V DC bus, 125 V battery, 100 A AC current), whereas reverse power flow yields positive output impedance with superior stability margins—a critical distinction for bidirectional PCS operation in battery energy storage systems. • • The proposed capacitor current observer eliminates the need for high-precision current sensors, reducing hardware cost while achieving effective impedance reshaping; experimental waveforms under condition 3 show bus voltage oscillation suppression within 40 ms and stable 800 V regulation, confirming practical viability for commercial PCS. • • Impedance optimization reduces the source converter output impedance resonant peak and weakens the load converter negative impedance, preventing impedance magnitude intersection; this expands the stable operating range of the two-stage PCS, validated by experimental results showing consistent performance with simulations under 200 ms time scale and 100 V/div bus voltage resolution. • • The study establishes that stability degradation in two-stage PCS arises from cascaded coupling effects often neglected in single-stage designs; the bidirectional impedance models for DC/DC and VSC provide a generalizable framework for analyzing and mitigating oscillations in renewable energy integration and microgrid applications.