Oxide-channel ferroelectric transistor enables ultralow-power NAND flash technology
The escalating power consumption of 3D NAND flash memory, driven by the need for high pass voltages (V_pass) to read cells in vertically stacked strings, poses a critical challenge as layer counts approach 1000. Conventional charge-trap NAND requires V_pass of 5–10 V for quad-level cell (QLC) operation, while silicon-channel ferroelectric NAND suffers from limited memory windows due to low-k interlayers. Here, we highlight a breakthrough by Yoo et al. that introduces an oxide semiconductor (OS)-channel ferroelectric field-effect transistor (FeFET) with a gate stack comprising a zirconium-doped hafnium oxide (HZO) ferroelectric layer sandwiched between low-k (SiO2/SiNx) and high-k (Ta2O5) interlayers, and an indium gallium zinc oxide (IGZO) channel. The absence of hole carriers in IGZO suppresses the 'down' polarization state, enabling a near-zero threshold voltage (V_th) and reducing V_pass to as low as 1 V. The high-k Ta2O5 interlayer prevents oxygen diffusion, mitigating off-current degradation, while the low-k SiO2/SiNx interlayer enhances charge trapping, yielding a memory window exceeding 11 V for a 5-nm SiO2 layer. This enables 5-bit-per-cell (penta-level cell, PLC) operation, surpassing current QLC NAND. The combination of ultralow V_pass and wide memory window achieves both low power consumption and high storage density, positioning OS-channel FeFETs as a promising solution for next-generation memory systems.