Key Takeaways & Executive Findings
- •• • Ferroelectric tunnel junctions (FTJs) based on Hf0.5Zr0.5O2 (HZO) achieve sub-nA operating currents (e.g., <1 nA) and fast switching speeds, enabling high-density, low-power artificial synapses for deep learning acceleration (Ref. 191). • • Ultrathin (3.5 nm) ferroelectric tunnel junctions demonstrate energy-efficient reservoir computing for temporal data learning, with robust performance metrics suitable for edge AI applications (Ref. 201). • • In-plane charged domain walls in ferroelectric films exhibit memristive behavior, offering a novel mechanism for analog synaptic weight modulation with potential for high-density crossbar arrays (Ref. 195). • • Ferroelectric domain wall memories and FTJs show enhanced tunneling electroresistance (TER) ratios, with values exceeding 1000% in optimized heterostructures, crucial for reliable multi-state storage in neuromorphic systems (Ref. 187).
Abstract
The rapid expansion of artificial intelligence (AI) model sizes to trillions of parameters has intensified the demand for computational paradigms that overcome the von Neumann bottleneck. Emerging memory technologies, while advancing, fall short of meeting the massive requirements of large-scale models. Ferroelectric materials, with their continuous tunability of domain patterns, offer a promising route to emulate synaptic weights in biological learning. This review systematically examines four fundamental ferroelectric-based device architectures: ferroelectric capacitors, ferroelectric field-effect transistors (FeFETs), ferroelectric tunnel junctions (FTJs), and ferroelectric domain wall memories. We analyze their latest progress, application domains, and inherent advantages, while critically assessing the challenges impeding their commercialization. Key issues include scalability, endurance, retention, and integration with CMOS technology. We also highlight optimization strategies for material and device performance, array-level design, and neuromorphic computing architectures. Future research directions are proposed, emphasizing the expansion of novel applications and the realization of energy-efficient, high-density in-memory computing systems. This review provides a comprehensive framework for researchers and engineers aiming to harness ferroelectric devices for next-generation computing.
1. Introduction
The exponential growth of global data—projected to reach 393.8 ZB by 2028—and the escalating computational demands of AI, increasing at over twice the rate of Moore's Law, have exposed the fundamental limitations of conventional von Neumann architectures. The physical separation of memory and processing units creates a 'memory wall' bottleneck, throttling performance and energy efficiency. While CMOS technology dominates integrated circuits, implementing synaptic plasticity for neuromorphic computing with CMOS components requires prohibitive area consumption, rendering it impractical for large-scale neural networks. This impasse necessitates a paradigm shift toward in-memory computing and neuromorphic architectures that unify memory and computation.
Ferroelectric-based devices emerge as a compelling solution due to their intrinsic ability to continuously modulate domain patterns, mimicking synaptic weights in biological systems. This review focuses on four device types—ferroelectric capacitors, FeFETs, FTJs, and domain wall memories—each offering unique advantages in speed, endurance, and scalability. However, challenges such as material stability, device-to-device variability, and integration with existing CMOS processes remain. By critically analyzing recent experimental breakthroughs and identifying key optimization pathways, this work aims to guide the development of ferroelectric devices toward practical neuromorphic computing applications, addressing the urgent need for energy-efficient, high-density computational hardware.
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WANG Xinglong, SONG Jiankang, NING Zhongfeng, ZHANG Wendi, JIANG Anquan (2026). Thriving In-Memory Computing and Neuromorphic Applications of Ferroelectric-Based Devices. SCIENCE CHINA Materials. https://doi.org/10.1007/s40843-025-3874-1
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Frequently Asked Questions
What are the primary failure mechanisms limiting the endurance of ferroelectric tunnel junctions (FTJs) under repeated switching, and how do they compare to FeFETs?
FTJs suffer from fatigue and imprint due to charge trapping at the ferroelectric-electrode interfaces and oxygen vacancy migration, leading to reduced tunneling electroresistance (TER) over cycles. FeFETs face similar issues but also encounter charge trapping in the semiconductor channel, which can cause threshold voltage shifts. For HZO-based FTJs, endurance up to 10^8 cycles has been demonstrated, but further improvements require interface engineering and defect passivation.
How do ferroelectric domain wall memories achieve multi-state storage, and what is the maximum number of distinct resistance states reported?
Ferroelectric domain wall memories utilize the controlled motion of charged domain walls, which exhibit distinct resistance states depending on wall orientation and density. By applying voltage pulses of varying amplitude and duration, multiple intermediate resistance levels can be programmed. Recent studies have demonstrated up to 32 distinct states in in-plane charged domain wall devices, enabling high-density analog synaptic emulation.
What are the scalability challenges for integrating ferroelectric devices into crossbar arrays for in-memory computing, particularly regarding sneak path currents and device variability?
Crossbar arrays suffer from sneak path currents that can corrupt read operations. Ferroelectric devices with high resistance ratios (e.g., >100) mitigate this issue, but device-to-device variability in switching voltages and resistance states remains a challenge. For HZO-based FTJs, sub-nA currents reduce power consumption but require precise control of film thickness and electrode interfaces to ensure uniformity. Advanced selector devices or transistor-per-cell architectures may be necessary for large arrays.
Can ferroelectric devices achieve the energy efficiency required for edge AI applications, and what are the typical energy consumption per synaptic operation?
Yes, ferroelectric devices, particularly FTJs, have demonstrated energy consumption as low as a few femtojoules per switching event. For example, HZO-based FTJs with sub-nA currents and fast switching speeds enable energy-efficient synaptic operations. Reservoir computing systems using ultrathin FTJs have shown robust performance with minimal energy overhead, making them suitable for edge devices where power is constrained.
What are the main obstacles to commercializing ferroelectric-based neuromorphic chips, and what recent advances address these?
Key obstacles include material compatibility with CMOS processes, especially for HfO2-based ferroelectrics, which require careful doping and annealing. Scalability to advanced nodes (<28 nm) is challenging due to ferroelectric phase stability. Recent advances in atomic layer deposition (ALD) of HZO and the development of 3D integration schemes have improved compatibility. Additionally, the demonstration of reliable operation in array-level prototypes has increased maturity, but further work is needed to reduce variability and improve endurance to meet industrial standards.
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