• • Surface ΔT and effective junction ΔT are distinct quantities; device-level ΔT is generally smaller than surface ΔT because contact thermal/electrical resistance at electrodes and interfaces, plus nonuniform heat spreading, dissipates the gradient before it reaches the TE legs. Industrial consequence: TEG datasheets reporting only surface ΔT overstate usable power, and system integrators must demand a ΔT-transfer ratio under load to size modules correctly.
• • Reducing fill factor raises thermal resistance and can preserve junction ΔT, but it simultaneously increases electrical resistance and may reduce current output. This is a direct design trade-off: for a fixed leg material, the fill-factor optimum is bounded by the parasitic electrical penalty, so module geometry cannot be optimized independently of the spectral surfaces and environmental heat-transfer paths.
• • The TE module thermal resistance must be matched to the effective thermal resistance of the hot- and cold-side spectral surfaces and their environmental heat-transfer paths, rather than optimizing either component in isolation. Mismatch causes the spectral ΔT to be dropped across interfaces instead of across the TE legs, collapsing load-matched power even when optical performance is excellent.
• • Night-time reversal of heat-flow direction through the PDRC/PT stack requires a DC polarity-conversion circuit to maintain output polarity, and dynamic load matching is mandatory because both open-circuit voltage and internal electrical resistance change with ΔT across day-night and weather variations. Without these power-electronics functions, all-day continuity fails regardless of material performance.