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Open AccessDOI: 10.1007/s40843-025-3773-7Original Research

Efficient CZTSSe Solar Cells with the Highest VOC of 591 mV Enabled by Thermal Sputtering ITO

Key Laboratory for Special Functional Materials of Ministry of Education, School of Materials Science and Engineering, Henan University

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Efficient CZTSSe Solar Cells with the Highest VOC of 591 mV Enabled by Thermal Sputtering ITO
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SCIENCE CHINA Materials
Published:January 15, 2026Edition:Vol. 69, Issue 3 • pp. 100-112Citation:Tong Liu et al. (2026), SCIENCE CHINA Materials
Impact Factor3.5 (Q2 Scopus)
Source Journal中国科学: 材料
Strategic Intelligence Pillar
Perovskite Solar Cells: Silicon/Perovskite Tandem Cells, 2D/3D Passivation & Module Stability
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Key Takeaways & Executive Findings

  • • • Champion device achieved a power conversion efficiency (PCE) of 14.29%, with an open-circuit voltage (VOC) of 591 mV, the highest reported for CZTSSe solar cells to date, directly addressing the VOC deficit bottleneck. • • The low-temperature annealing during ITO sputtering (SA) improved ITO crystallinity, carrier concentration, and optical transmittance, while promoting In diffusion into CdS and CZTSSe layers, leading to an optimized ITO/In:CdS/In&Cd:CZTSSe heterojunction with favorable band alignment. • • The SA treatment enabled epitaxial growth at the CZTSSe/CdS interface by optimizing lattice matching, which reduces interfacial recombination and enhances carrier transport, critical for achieving high VOC. • • The study demonstrates a synergistic approach to interface engineering and defect passivation, providing a pathway to overcome the efficiency gap between CZTSSe and CIGS technologies, with potential for industrial scalability.

Abstract

Kesterite Cu2ZnSn(S,Se)4 (CZTSSe) solar cells suffer from significant open-circuit voltage (VOC) deficits due to severe interfacial and bulk recombination, restricting their power conversion efficiency (PCE) far below the Shockley-Queisser limit. This work proposes a low-temperature annealing strategy during ITO sputtering (SA) to synergistically address these challenges. The temperature applied during ITO sputtering not only improves the crystallinity, carrier concentration, and optical transmittance of the ITO layer but also promotes the diffusion of In from ITO into both CdS and CZTSSe layers. Consequently, lattice matching at the CZTSSe/CdS interface is optimized, enabling epitaxial growth. And a favorable ITO/In:CdS/In&Cd:CZTSSe structure with optimal band alignment is obtained. As a result, a champion device with a PCE of 14.29% was achieved. The SA-treating also enabled the CZTSSe solar cells to achieve the highest VOC reported to date, exceeding 590 mV. This underscores the essential role of SA processing in optimizing interface engineering and suppressing defects, thus promoting the development of low-cost, high-performance kesterite photovoltaics.

1. Introduction

Kesterite Cu2ZnSn(S,Se)4 (CZTSSe) solar cells have attracted considerable attention in new-generation thin-film photovoltaics due to their high optical absorption coefficient (>10^4 cm^-1), tunable direct bandgap (1.0–1.5 eV), and economic, environmentally friendly attributes. However, their power conversion efficiency (PCE) remains significantly below the Shockley-Queisser limit (32%) and that of predecessor Cu(In,Ga)(S,Se)2 (CIGS) technology (23.64%). The principal impediment is the substantial open-circuit voltage (VOC) deficit, attributed to severe nonradiative recombination at the CdS/CZTSSe heterojunction interface. Among interfacial factors, the conduction band offset (CBO) plays a critical role in carrier transport and recombination. While a small spike-type CBO is beneficial, an excessively large CBO (>0.4 eV) acts as an energy barrier, impeding electron transport. Additionally, poor crystallinity of chemical-bath-deposited CdS and abundant intrinsic defects (e.g., CuZn, SnZn, [SnZn+2CuZn]) in CZTSSe contribute to defective interfaces and non-radiative recombination centers, limiting built-in potential and VOC.

To address these challenges, heterojunction heat treatment (JHT) has been recognized as an effective technique for chalcogenide solar cells. This work introduces a low-temperature annealing strategy during ITO sputtering (SA) that synergistically improves the ITO layer properties and promotes In diffusion into both CdS and CZTSSe layers. This dual effect optimizes lattice matching at the CZTSSe/CdS interface, enabling epitaxial growth and forming a favorable ITO/In:CdS/In&Cd:CZTSSe structure with optimal band alignment. The SA treatment not only enhances crystallinity, carrier concentration, and optical transmittance of ITO but also suppresses interfacial defects, leading to a champion device with a PCE of 14.29% and a record VOC of 591 mV. This approach underscores the essential role of SA processing in interface engineering and defect passivation, offering a promising route to high-performance, low-cost kesterite photovoltaics.

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Cite This Research Paper
Tong Liu, Litao Han, Lunan Pei, Xinyi Zhong, Wentong Yang, Kelin Leng, Qiang Zeng, Dongxing Kou, Zhengji Zhou, Fangyang Liu, Sixin Wu (2026). Efficient CZTSSe Solar Cells with the Highest VOC of 591 mV Enabled by Thermal Sputtering ITO. SCIENCE CHINA Materials. https://doi.org/10.1007/s40843-025-3773-7
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Frequently Asked Questions

What is the specific role of the low-temperature annealing during ITO sputtering in improving the VOC of CZTSSe solar cells?

The SA treatment promotes In diffusion from ITO into both CdS and CZTSSe layers, which optimizes the conduction band offset and lattice matching at the heterojunction interface. This reduces interfacial recombination and enables epitaxial growth, leading to a record VOC of 591 mV and a PCE of 14.29%.

How does the SA treatment affect the electrical and optical properties of the ITO layer?

The SA treatment improves the crystallinity, carrier concentration, and optical transmittance of the ITO layer, which are critical for efficient carrier collection and light transmission in the solar cell stack.

What are the key mechanisms by which In diffusion into CdS and CZTSSe layers enhances device performance?

In diffusion into CdS and CZTSSe layers modifies the band alignment, creating a favorable ITO/In:CdS/In&Cd:CZTSSe structure. This reduces the CBO barrier, suppresses interfacial defects, and improves carrier transport, thereby increasing VOC and overall efficiency.

How does the SA treatment compare to conventional heterojunction heat treatment (JHT) in terms of process temperature and impact on device performance?

The SA treatment is performed at low temperatures during ITO sputtering, which is compatible with industrial processes. It provides synergistic benefits by simultaneously improving the ITO layer and the heterojunction interface, whereas conventional JHT typically requires separate annealing steps. The SA treatment achieved a record VOC of 591 mV, demonstrating its effectiveness.

What are the potential scalability and cost implications of the SA treatment for commercial CZTSSe solar cell production?

The SA treatment is a low-temperature process that can be integrated into existing sputtering systems, potentially reducing manufacturing complexity and cost. By achieving higher efficiencies, it enhances the economic viability of CZTSSe technology, making it more competitive with CIGS and other thin-film photovoltaics.

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